In December 2025, a momentous—yet remarkably quiet—turning point arrived for the global semiconductor industry. TSMC (Taiwan Semiconductor Manufacturing Company), the world's largest foundry, officially began mass production (HVM: High Volume Manufacturing) of its next-generation 2nm process (N2).
This news was conveyed to the world not through a flashy press conference or a major press release, but "quietly," in the form of a brief statement update on the company's technology webpage. Yet this very silence eloquently speaks to TSMC's absolute confidence in its technology and to the fact that production capacity has already been fully booked by major customers such as Apple and NVIDIA.
The Silent Giant's Move: Mass Production Begins Without a Press Release
TSMC's "2nm Technology" page currently carries the following sentence:
"TSMC's 2nm (N2) technology entered volume production in the fourth quarter of 2025 as planned."
This concise declaration means the company has perfectly adhered to the roadmap it has maintained for years. Normally, the launch of a new process node is a prime opportunity for a company to showcase its technological prowess, but the fact that TSMC settled for a mere administrative update suggests two possible reasons:
- Overwhelming demand and fully booked capacity: Initial production capacity has already been completely secured by major customers such as Apple and NVIDIA, leaving no need for further promotional activity.
- A display of confidence: The confidence that comes from having executed, without trouble and on schedule, the transition to the GAA structure—known to be an extremely difficult development challenge—made excessive fanfare unnecessary.
Beyond the Limits of FinFET: The First GAA "Nanosheet" Transistors
The greatest technological innovation of the N2 process lies in the fact that it finally abandons the "FinFET structure," which had been the industry standard for over a decade, in favor of GAA (Gate-All-Around) nanosheet transistors.
From FinFET to GAA: What Changes?
Conventional FinFET had a structure in which the gate covered three sides of the channel through which current flows. However, as the process shrank below 3nm, controlling the current (particularly cutting off leakage current) became physically difficult—a limitation the industry faced head-on.
By contrast, the GAA structure adopted by TSMC in N2 has the gate completely surrounding all four sides of stacked horizontal nanosheets (channels). This yields the following benefits:
- Dramatic improvement in electrostatic control: Because the gate fully commands the channel, off-state leakage current can be reduced to an extreme minimum.
- Design flexibility (NanoFlex): By adjusting the width of the nanosheets, it becomes possible to mix "high-performance-focused" transistors and "low-power-focused" transistors within the same chip.
Stabilizing Power Delivery with SHPMIM Capacitors
In addition to the overhaul of the transistor structure, N2 also introduces an innovation to the power delivery network (PDN): the adoption of "Super High-Performance Metal-Insulator-Metal (SHPMIM)" capacitors.
This new capacitor boasts more than double the capacitance density compared to conventional designs, while reducing sheet resistance (Rs) and via resistance (Rc) by 50%. This is an extremely important factor in preventing voltage drops and enhancing operational stability in chips that consume large amounts of power, such as AI processors.
N2's Performance by the Numbers: The "Holy Grail" of the AI Era
TSMC's published performance metrics for N2, compared against the N3E process (an enhanced 3nm), do not disappoint industry expectations.
- Power reduction: 25%–30% less at the same performance
- Performance improvement: 10%–15% more at the same power
- Density improvement: 15% or more for mixed designs (logic, SRAM, analog), and 20% for logic alone
What a "30% Power Reduction" Truly Means
Of particular note is the magnitude of the power reduction. Currently, the biggest bottleneck in generative AI training and inference is not "computational power" but "power supply" and "heat generation." The fact that a data center can perform 30% more computation within the same power budget—or accomplish the same computation using 30% less power—will literally be a "holy grail" for NVIDIA's next-generation GPUs (such as Rubin Ultra) and for Apple's on-device AI features.
An Unusual Manufacturing Strategy and a Remarkable "70%" Yield
Early Mass Production at Fab 22 (Kaohsiung)
Interestingly, it has been reported that this N2 chip mass production began not at Fab 20 (adjacent to the R&D center) in Hsinchu in northern Taiwan, but at Fab 22 in Kaohsiung in the south. This overturns TSMC's traditional formula of launching a process in Hsinchu first and then expanding to other sites. This suggests a flexible and aggressive strategic shift by the company—one aimed at immediately bringing an available new fab to full operation in order to meet the surge in AI demand.
Simultaneous Launch for Mobile and HPC
Normally, a new process would first launch with smartphone SoCs (such as Apple's A-series), where yield management is relatively easier, before moving on to more complex HPC (high-performance computing) chips. However, according to remarks by CEO C.C. Wei, N2 has adopted the unusual approach of launching smartphone and AI/HPC applications simultaneously. This also serves as evidence of just how immense the market's hunger for AI accelerators has become.
70% Yield: A Decisive "Moat" Against Samsung and Intel
According to reports, the yield for logic chips at the Hsinchu and Kaohsiung facilities has already reached 70%.
A figure of 70% at this early stage, with a completely new transistor structure (GAA), can only be described as extraordinary. Rival Samsung was quick to introduce GAA at the 3nm generation, but suffered from sluggish yields, resulting in major customers such as Qualcomm being lost to TSMC. Intel also aims to make a comeback with its "18A" process, but TSMC's stability and scale of mass production will function as a massive "moat" that other companies cannot easily overcome.
Economics and Geopolitics: A World Order Centered on Silicon
Alongside this technological triumph, economic hurdles are rising. The cost per wafer is estimated to reach approximately $30,000 (roughly ¥4.5 million), a sharp increase even compared to previous nodes.
This cost increase will likely accelerate the adoption of "chiplet technology." In other words, the approach of manufacturing only the most critical compute cores at 2nm, while producing I/O and cache memory components using cheaper, older-generation processes (such as 5nm or 6nm) and then packaging them together, is set to become the standard going forward.
Additionally, the concentration of leading-edge processes in Taiwan's Kaohsiung and Hsinchu once again highlights geopolitical risks (such as a potential Taiwan contingency). The fact that the fate of global AI development rests in the hands of a handful of factories in Taiwan is unlikely to change anytime soon, despite ongoing efforts by the United States and others to diversify the supply chain.
The Roadmap Ahead: Toward N2P and A16
TSMC's innovation does not end here. The company is already preparing extended versions of N2 technology.
- N2P (second half of 2026): An enhanced-performance version of N2.
- A16 (second half of 2026–2027): A process equivalent to 1.6nm. Here, the Backside Power Delivery (BSPDN) technology known as "Super Power Rail (SPR)" will be introduced.
SPR is a technology that resolves congestion in wiring layers and delivers power directly from the backside of the wafer, achieving even greater density and suppressing voltage drops. With this technology—positioned as a rival to Intel's "PowerVia"—being deployed, Moore's Law will slip past the wall of physical limits, extending its life into the 2030s.
The Foundation for a New AI Era Is Complete
TSMC's start of mass production of the 2nm process is not simply news that "chips have gotten smaller." It means that the AI industry, which had been confronting a wall of power efficiency, has now obtained the physical foundation for another round of accelerated evolution.
The advanced agentic AI realized by Apple's next-generation iPhones (such as the iPhone 18 Pro/A20 chip) and the knowledge models processed at civilization-scale by NVIDIA's next-generation data centers will all run atop the "N2 silicon" produced at these factories in Kaohsiung and Hsinchu.
We should remember that the technological evolution we will witness in 2026 traces its origins back to this quiet start of mass production in late 2025.
Sources
- TSMC: 2nm Technology