TSMC is working to bring cooling for AI advanced packages closer to the silicon surface, moving away from external components. According to Taiwan's Economic Daily News, James Chen, head of advanced packaging R&D, revealed at a forum associated with SEMICON Taiwan 2026 on September 1, 2026, that microchannel cooling has been added to the company's research roadmap. CnYes reported his outlook that future CoWoS package power could rise from roughly 600W to 4,100W.
TSMC has already reported test vehicles at academic conferences that dissipate 3.4kW in 2025 and over 5kW in 2026 using CoWoS-R structures. The capability to cool 4,100W-class packages is already emerging in the lab. The main uncertainty ahead now shifts to manufacturing: whether the same structure can be reproduced repeatedly without leaking coolant, without warping expensive large packages, and while handling localized heat generation.
What the 6x Figure Actually Refers To
The roughly "6x" figure Chen presented is not a forecast for overall AI data center power demand. According to CnYes, it is an estimate that CoWoS package power will rise from about 600W to 4,100W between 2024 and 2029. Over the same period, CoWoS area is expected to expand from roughly 3.3 reticle-equivalent to more than 14 reticles, the number of compute transistors within a package is expected to increase roughly 48-fold, and HBM bandwidth is expected to exceed 34 times current levels.
TSMC's official roadmap from April 2026 also supports this trend toward larger packages. The company is currently producing 5.5 reticle-equivalent CoWoS, and plans call for a 14 reticle-equivalent product carrying roughly 10 large compute dies and 20 HBM stacks by 2028, with products exceeding 14 reticles arriving in 2029. As more silicon is packed in, total power rises. As stacking and high-density interconnects bring heat sources closer together, hot spots—localized areas where temperature rises sharply—become more severe even at the same 4,100W total.
The 48x transistor count and 34x memory bandwidth figures do not automatically determine the thermal design for 4,100W. These are three separate metrics, and package power cannot be directly calculated from transistor count or bandwidth alone. The 4,100W figure itself is a presentation value based on an assumed future single package, not the rated power consumption of a shipping product.
As a point of comparison, NVIDIA's current DGX GB rack consumes about 120kW. The rack houses 18 compute trays and 9 NVLink switch trays, among other components, with manifolds delivering coolant to individual CPU and GPU cold plates. The 4,100W figure represents package-level power within that system—it is not a forecast that overall rack power will increase sixfold. Even if heat is captured near the chip, the work of distributing coolant within the rack and carrying heat out to the facility side remains.
Cold Plates, Channel-Integrated Lids, and Direct-to-Silicon Cooling
In today's high-power GPUs, a common structure presses a coolant-carrying cold plate against the top of the package. Between the die and the coolant sit a thermal interface material (TIM), a metal lid, and sometimes another layer of TIM. While TIM fills microscopic gaps on surfaces, it also adds thermal resistance depending on thickness and contact quality. As heat generation increases, the temperature difference created by even a single material layer becomes harder to ignore.
TSMC's vision for bringing cooling closer involves structurally distinct stages.
| Stage | Where Coolant Flows | Heat Path Eliminated | New Responsibilities |
|---|---|---|---|
| External Cold Plate | On top of package lid | Current baseline | Cold plate compression, TIM management |
| Channel-Integrated Lid | Inside package exterior | Cold plate-to-lid interface | In-lid channels, connection sealing |
| Direct-to-Silicon Cooling | Micromachined die backside | Path through lid and TIM | Silicon processing, channel formation, leak testing |
Cooling evolution can be divided into three stages: external cold plate, channel-integrated lid, and direct-to-silicon cooling. Each material layer removed between the heat source and coolant reduces thermal resistance, but expands the scope of responsibility the semiconductor package itself must take on—channels, sealing, and leak testing. That said, lid, TIM, and cold plate configurations vary by product, and there's no guarantee all three stages will be adopted in the same order or timeline.
"Microchannel" is a broad term that can encompass the latter two of these three stages. Carving fine water channels into a lid and forming microscopic pillars on the die backside to flow coolant directly are not the same structure. Jet impingement cooling, mentioned in the presentation, sprays coolant onto the heat-generating surface, while two-phase cooling uses latent heat during boiling—both represent design axes separate from where the channel itself is placed.
Beyond 5kW Already Demonstrated, Ahead of the 4,100W Forecast
TSMC's two papers verify not only heat dissipation capacity but also CoWoS integration and sealing reliability under different conditions.
| Presentation | Test Vehicle and Coolant | Flow Rate | Published Uniform Heat Dissipation | Reliability Verification |
|---|---|---|---|---|
| ECTC 2025 | 3.3 reticle-equivalent CoWoS-R, 40°C water | 10 liters/min | 3.4kW, 2.5 W/mm² | 3 reflow cycles, 2,000 temperature cycles, 1,000 hours storage at 150°C, and more |
| ECTC 2026 | 3.3 reticle-equivalent CoWoS-R, 40°C deionized water | 6 liters/min | Over 5kW, 3.7 W/mm² | No degradation in helium leak rate or sealant delamination after MSL4 preconditioning |
| September 2026 Presentation Forecast | Future single CoWoS package | Not disclosed | Approximately 4.1kW | Conditions for customer products not disclosed |
Comparing TSMC's published figures: the 2025 test vehicle processed 3.4kW while flowing 40°C water at 10 liters per minute, while the 2026 test vehicle handled over 5kW at 6 liters per minute. The 4.1kW future package power figure presented in the talk is already within reach if we consider only the heat dissipation capacity of the research test vehicles.
The 3.7 W/mm² figure shown by TSMC's 2026 test vehicle equates to 370 W/cm². However, this is a test value from applying uniform power to a heat source equivalent to 1.6 reticles—it is not the allowable power consumption for a production GPU with localized hot spots. Because microstructure and flow rate also differ between 2025 and 2026, the change from 3.4kW to over 5kW cannot be calculated as a performance improvement ratio under identical conditions.
Both papers also address sealing reliability and manufacturing processes. The 2025 research established a critical annual leak rate of 115cc based on typical data center environments. Helium leak rates after various reliability tests were at least an order of magnitude below that critical value. In 2026, the team adopted a sealant that follows warpage, and developed dedicated wafer carriers and jigs for forming microscopic pillars on the SoC backside, handling everything from CoWoS front-end processing through assembly as an integrated process. Both years' work addresses CoWoS integration, with the 2026 paper further detailing the processing and sealing steps.
Can It Be Made Without Leaks, Without Warping, and at Scale?
The first remaining challenge from the over-5kW test vehicle is uneven heat generation. In actual AI accelerators, compute dies, HBM, and power circuits do not generate heat at the same flux. Uniform heat generation test values alone don't reveal the maximum junction temperature under localized hot spots and flow distribution. The values TSMC needs to show next, beyond total heat dissipation, include maximum junction temperature under power distributions that mimic real chips, pressure loss, and pump power.
Second is package yield after adding cooling structures. Even if sealing can be maintained in a 3.3 reticle-equivalent test vehicle, the 14 reticle-equivalent products planned for 2028 will have larger area and more material interfaces. The larger structure must still achieve warpage-following seals, uniformly process microscopic pillars, create leak-free connections, and undergo inspection without damaging expensive compute dies.
Third is the division of responsibility from package to rack. NVIDIA's current rack keeps manifolds, cold plates, and leak detection on the system side. With direct-to-silicon cooling, channels formed during semiconductor processing must connect to rack-side piping. Which party—package makers, cooling component makers, or server makers—will take responsibility for coolant quality and connections? Field replacement procedures and long-term leak warranties will also need to be built into product specifications.
That the shift to mass production is a shared challenge is evident from moves beyond TSMC as well. An HP project supported by the U.S. ARPA-E, running from 2024 to 2027, first bonds silicon microchannels to device surfaces before progressing to a stage where they're embedded further inside. SEMI committee materials also note the need to establish, across the industry, the maturity of necessary processes and test vehicles suited for commercialization.
If TSMC discloses the timeline for customer product adoption and coolant inlet conditions, the over-5kW test vehicle will turn into a product roadmap. Allowable leak rates, connector specifications, and yield from added processes will also serve as judgment criteria. Once those conditions are in place, AI packages will no longer be components cooled from the outside, but systems where the cooling path is designed alongside power delivery from the same stage.