On August 24, 2026, Xiaomi announced its second-generation self-designed flagship SoC, the XRING O3. While keeping the same 3nm manufacturing generation, the company expanded the die to 133mm² and overhauled everything from the 10-core CPU to the GPU, NPU, and memory pathways at once. The official AnTuTu V11 score reaches 5,228,014 points—though it's worth noting this is a peak value measured in a cooled laboratory environment. To gauge the real-world capability of the XRING O3, it's more useful to separate the mechanism that feeds data smoothly to the increased number of execution units from the performance that remains once you factor in the power budget a smartphone can actually sustain, rather than focusing on the size of the benchmark score alone.
Same 3nm process, but the die grew 22% larger
The XRING O3 packs 24 billion transistors into 133mm². The first-generation XRING O1 had 19 billion transistors on 109mm², meaning transistor count rose by roughly 26% and area by roughly 22%. A simple calculation from the published figures shows transistor density rising from about 174 million to about 180 million per mm²—an increase of roughly 3.5%—but since both the area and transistor counts are rounded figures, this isn't a number from which precise cell density can be reverse-engineered.
| Item | XRING O1 | XRING O3 | Change |
|---|---|---|---|
| Process | 2nd-gen 3nm | 3nm | Same 3nm generation |
| Die area | 109mm² | 133mm² | Up ~22% |
| Transistor count | 19 billion | 24 billion | Up ~26% |
| CPU | 10 cores, 4 clusters | 10 cores, 3 clusters (no efficiency cores) | Efficiency cores removed |
| GPU | 16-core Immortalis-G925 | 16-core G2-Ultra NX | New-generation IP with AI accelerators |
| NPU | 6 cores, 44TOPS | 4 cores, 200TOPS (A8W4) | Redesigned for large models |
| Memory | LPDDR5-series | LPDDR6 / LPDDR5X | Up to 113.8GB/s |
| Key caches | Not disclosed | 60MB total | 16MB SLC added |
What this table reveals is a design philosophy that expanded usable die area within the same manufacturing generation, rather than simply shrinking through finer lithography. Semiconductor analysis firm Geekerwan has identified the process as TSMC's N3P, though Xiaomi itself only confirmed "3nm" during its press event. According to TSMC, N3P offers up to 5% higher speed at the same leakage current compared to N3E, or 5-10% lower power consumption at the same speed, along with 1.04x the density. These figures alone can't account for the performance gaps Xiaomi claims—60% for the CPU and 85% for the GPU.
Much of the gain appears to stem from circuit-level design choices. Geekerwan's die analysis found that the XRING O3 tightened the routing areas between functional blocks and designed more than 2,400 custom cells beyond TSMC's standard cell library. Even when adopting Arm's CPU and GPU IP, it's Xiaomi that decides core counts and cache capacity, and designs the routing and power management. Physical layout is also Xiaomi's own work. The larger 133mm² die trades performance for increased manufacturing cost and yield pressure. And since the die doesn't include a 5G baseband, the total board area and power required at the device level exceed what the SoC figures alone suggest.
Ten high-performance CPU cores deliver speed, but 20W is a dev-board peak
The CPU runs two C1-Ultra cores at 4.35GHz, four C1-Premium cores at 3.68GHz, and four C1-Pro cores at 3.15GHz. All are Armv9.3-generation cores, and there's no dedicated low-load C1-Nano core. That said, this doesn't mean all 10 cores are identical large cores. The C1-Ultra handles bursts of single-thread performance, the C1-Premium—with its area trimmed by 35%—covers mid-level loads, and the C1-Pro handles sustained performance and low-power operation.
According to generational comparisons Arm shared when announcing the IP, the C1-Ultra delivers 25% higher single-thread performance than the Cortex-X925. The C1-Pro also offers 16% higher sustained performance than the Cortex-A725 at the same clock speed, and can hit the same performance using up to 12% less power. The XRING O3 arranges these three tiers as 2+4+4 cores, dropping the Cortex-A520-class efficiency cores that were present in the O1. The goal is to increase parallel processing under heavy loads while handing off everyday workloads to the lower-clocked C1-Pro.
Xiaomi's published Geekbench 6.5 scores show 3,945 single-core and 15,221 multi-core—up roughly 31% and 60%, respectively, from the O1 comparison figures shown at the press event. The company also states that CPU power consumption under low-to-moderate loads dropped by up to 25%. The effect of stacking 10 cores shows up most clearly in multi-core performance. The gap between the 31% single-core gain and the 60% multi-core gain reflects not just higher clock speeds but also the greater number of large cores that can now work simultaneously.
In power-performance curves for SPEC CPU 2026 that Geekerwan measured on a development board, the C1-Ultra outperformed comparable Android SoCs and approached the Apple A19 Pro. Geekerwan also reported that the C1-Pro reached the same peak performance as the identical core in the Dimensity 9500 while using roughly half the power. However, the published analysis doesn't reveal compiler settings or the exact scope of the power measurements. Within the bounds of this measurement, it's fair to say that even with identical Arm IP and the same 3nm process generation, Xiaomi's implementation produced a measurable performance difference.
That said, Geekerwan reported that the development board's CPU drew roughly 20W when Geekbench exceeded 15,000 points. The published analysis doesn't specify detailed methodology, including which power rails were measured, so this figure can't be directly compared with other measurements. Similarly, the AnTuTu score of 5,228,014 measured in a cooled environment confirms that this peak performance exists, but doesn't tell us how many minutes a thin foldable device could sustain it. For production devices, the power-performance curve in the 5-10W range, surface temperature, and post-throttling scores will be the practical benchmarks that matter.
The G2-Ultra NX runs rendering and AI processing in the same place
The 16-core G2-Ultra NX marks the first public appearance of Arm's next-generation GPU, debuting in the XRING O3. According to Xiaomi, it supports Vulkan 1.4 and third-generation hardware ray tracing, and includes eight NX neural accelerators. Arm has not yet publicly disclosed the internal configuration of the G2-Ultra NX, so it's not yet possible to compare its execution unit count, clock speed, or texture processing capability against competing GPUs.
Xiaomi claims performance gains over the O1 of 94% in GFXBench Aztec Ruins 1440p, 85% in 3DMark Steel Nomad Light, and 182% in 3DMark Solar Bay Extreme's ray tracing test. Power consumption at the same performance point dropped by up to 64%. However, that 64% figure isn't an average across all games—it represents the maximum difference at a performance point Xiaomi selected. Driver maturity and game-side optimization will also affect real-world frame rates.
There is some independent evidence as well. Geekerwan's development board scored over 4,700 in Steel Nomad Light, and the company's power-performance curve showed roughly 2,500 points at 4.5W—a point on the curve that surpasses the O1's peak. However, the published analysis doesn't clarify how much of the power measurement covers the GPU alone versus the entire SoC, so the 4.5W figure shouldn't be treated as device-level power consumption. The development board also doesn't include a device chassis, battery, or radio components, so this isn't a preview of sustained performance on the Xiaomi 18 Fold.
The role of NX is to handle AI super-resolution and frame interpolation within the GPU itself. In conventional architectures, the GPU must send rendered images to the NPU via memory, then receive them back after processing. With NX, images can be processed near the rendering pipeline itself, reducing round-trip data and latency. The combined rated output of the eight units is 36TOPS, and Xiaomi says it achieved a 20% reduction in power consumption for 540p-to-1080p super-resolution, and maintained 120fps for 30 minutes while simultaneously using 3.2K super-resolution and frame interpolation. Since the target games, input latency, and image quality evaluation methods haven't been disclosed, real-world testing on supported titles will be necessary.
LPDDR6 and 60MB of cache behind the 113.8GB/s figure
The XRING O3 is the first announced smartphone SoC to support LPDDR6. It runs at 10.667GT/s per pin across four 24-bit channels. Xiaomi describes the effective bandwidth as 113.8GB/s, a 48% increase over the O1. A simple calculation of raw physical bandwidth ("10.667 × 96 ÷ 8") comes to about 128.0GB/s, but of the 288 bits transferred per burst in LPDDR6, only 256 bits are actual data. Multiplying 128.0GB/s by the 8/9 data ratio yields 113.8GB/s, matching the official figure.
LPDDR6's initial speed isn't dramatically different from the fastest LPDDR5X parts. The real difference lies in channel width and how channels are divided. JEDEC's JESD209-6 spec widens each channel from 16 bits to 24 bits and further splits it into two independently operable 12-bit sub-channels. This preserves small 32-byte access granularity while allowing only the sub-channels actually needed to be active, making it easier to boost bandwidth while letting unused circuitry rest during lighter workloads. SK hynix's initial LPDDR6, announced in March 2026, also runs at 10.7Gbps, offering 33% higher speed and more than 20% lower power consumption compared to LPDDR5X.
The receiving side has also grown. The XRING O3 includes 12MB of total CPU L2 cache, a 16MB shared L3, and a 16MB system-level cache (SLC). Combined with 16MB dedicated to the GPU and NPU, total key cache capacity reaches 60MB. Since data that remains in cache doesn't need to be fetched from LPDDR6, this reduces both latency and power draw simultaneously. The 16MB SLC in particular reduces redundant external memory access in scenarios where multiple execution units and the ISP need to work with the same data.
Xiaomi says it redesigned the upper metal routing layers connecting to the unified bus and memory controller, shrinking static memory latency to 82ns. On Geekerwan's development board, latency measured roughly 85ns at a 128MB data depth, and roughly 180ns at a 256MB depth with bandwidth load applied to other cores. Inter-core latency across all core combinations reportedly stayed under 80ns as well. Larger caches paired with wider memory bandwidth form a combination designed to keep the growing number of execution units from sitting idle while waiting for data.
For MiMo, 2.6-bit compression matters more than 200TOPS
The 4-core NPU has a rated performance of 200TOPS, with vector operations reaching 3.13TFLOPS. Here, the 200TOPS figure reflects the A8W4 condition—combining 8-bit activations with 4-bit weights. This differs in meaning from figures based on INT8-only operations or those leveraging sparsity, so comparing TOPS numbers alone against competitors' figures doesn't settle which is superior. The CPU's SME2 (3.5TOPS) and the GPU's NX (36TOPS) also involve different precision levels and use cases, and cannot simply be added together.
The real implementation shift lies in the fact that Xiaomi co-designed its on-device model, "MiMo," together with the NPU. Xiaomi built a quantized model that represents weights using five discrete values, combined with Huffman-coded lossless compression. This brought the average bit width down to 2.6 bits, reportedly cutting the memory bandwidth needed to read weights by 30%. Large language model inference often hits a ceiling determined not by raw compute speed but by how quickly weights can be moved from memory. LPDDR6 and the 16MB SLC widen the external pathway, while near-memory storage inside the NPU and 2.6-bit compression reduce the actual volume of data that needs to be moved to the execution units in the first place.
In Xiaomi's internal testing with MiMo-3B, prefill (input processing) was 40% faster and decode (text generation) was 45% faster than a comparable conventional flagship SoC, with 26% lower power consumption. However, the name of the comparison SoC, the context length used, and absolute tokens/second figures haven't been disclosed. Rather than fixating on the 200TOPS ceiling, these three conditions are what should be verified once production devices are available.
AI compute isn't concentrated solely in the NPU. The CPU has SME2, the GPU has NX, the ISP handles AI noise reduction in the RAW domain, the display circuitry performs AI super-resolution, and the audio DSP has its own dedicated AI engine. The fifth-generation ISP supports single-lens input up to 432 megapixels, simultaneous triple-camera processing at 64MP+64MP+50MP, and 4K/60fps AI night-mode noise reduction. Hardware decoding for H.266/VVC has also been added. By placing each processing task on circuitry close to where the data originates, the design aims to reduce the power cost of repeated round trips to the NPU and memory.
The remaining constraints are heat and connectivity. Geekerwan's analysis found that the XRING O3 uses a conventional PoP (Package on Package) configuration and does not integrate a 5G baseband on the die itself. Xiaomi states that total power consumption during 5G use dropped by more than 20% compared to the O1, but hasn't disclosed the baseband model or test conditions. Whether a CPU pushing toward 20W-class power and a large GPU can fit into a thin foldable device while keeping power under control—including the external baseband—remains to be seen. The numbers that will ultimately determine how well the XRING O3's design holds up are the sustained performance in the 5-10W range and cellular battery life on the Xiaomi 18 Fold, launching in September, and how many minutes peak performance can be sustained on the Pad 9 Pro Max, which has more room for heat dissipation.