At "Advancing AI 2026" on July 23, 2026, AMD revealed the HPC-oriented model in its 6th Gen EPYC 9006 series, the "EPYC 9006X SP7." According to AMD's published materials, certain variants reach clock speeds of up to 5.15GHz and offer up to 3x the L3 cache per core compared to the equivalent EPYC 9006 SP7. The maximum L3 capacity is 1,152MB, and the theoretical peak memory bandwidth is approximately 1.6TB/s.
According to Tom's Hardware, which reported on the on-site announcement, the maximum configuration disclosed has 96 cores, with launch expected in the latter half of 2027. While the standard EPYC 9006 SP7, with up to 256 cores, pursues thread density per rack, the 9006X is reported to top out at 96 cores, prioritizing cache, frequency, and memory bandwidth instead. The 1,152MB figure itself hasn't increased since the EPYC 9684X in 2023. What's changed this time is the move of that large-capacity cache onto the Zen 6-generation platform, with its higher clock speeds and greater bandwidth.
The 256-Core 9006 and 96-Core 9006X Serve Different Roles
The 6th Gen EPYC lineup splits CPUs from the same generation into four distinct lines. The EPYC 9006 SP7, with up to 256 cores/512 threads, is aimed at agentic workloads and high-density general-purpose servers. The EPYC 9006 SP8, ranging from 8 to 128 cores, is a low-power design intended for enterprise systems and power-constrained environments. The EPYC 9006 LP, which uses LPDDR, is positioned as the host CPU for rack-scale AI systems that feed data to GPUs.
Within this lineup, the 9006X SP7 is designated for HPC, technical computing, and data-intensive processing. AMD cites simulation and modeling, as well as large-scale analytics, search, and in-memory analytics, as target use cases. In these workloads, even if you pack in a large number of compute cores, those cores end up waiting if the required data doesn't arrive from cache or memory in time. The 9006X's maximum core count is a little under 40% of the standard 9006's, reflecting a design emphasis on both the amount of data placed close to each core and the supply rate from main memory.
AMD describes the 9006X's L3 capacity as offering "up to 3x per core" compared to the equivalent 9006 SP7. If you simply divide the top-end figures for each series, the 9006X's 1,152MB shared across 96 cores works out to 12MB per core, while the standard 9006's 1,024MB divided across 256 cores comes to 4MB per core. However, it's unconfirmed whether AMD's "up to 3x" figure is a direct comparison of these two top-end configurations. The actual cache-sharing units and CCD configuration have not yet been disclosed. Access latency and per-SKU capacity also remain unknown.
Even the standard 9006's 1,024MB is a large total L3 capacity for a server CPU. Still, a design that distributes cache broadly across 256 cores and one that concentrates 1,152MB across 96 cores are aimed at different kinds of workloads. The former suits throughput-oriented tasks running large numbers of independent jobs in parallel, while the latter is better suited to workloads that repeatedly reference the same data and are sensitive to the effects of round trips to memory.
Same 1,152MB as Genoa-X, but Different Frequency and Bandwidth
The comparison point that best captures where the 9006X stands is the top-tier EPYC 9684X from the Genoa-X generation. The 9684X also has 96 cores/192 threads and 1,152MB of L3 cache, using AMD 3D V-Cache. Looking purely at maximum L3 and core count, Venice-X shows no increase.
| Item | EPYC 9684X | EPYC 9006X's Announced Maximum |
|---|---|---|
| CPU Generation | Zen 4 (Genoa-X) | Zen 6 (Venice-X) |
| Max Core Count | 96 | Reportedly 96 |
| Max L3 Cache | 1,152MB | 1,152MB |
| Max Frequency | 3.7GHz | 5.15GHz for certain variants |
| Memory Channels | 12 | 16 |
| Max Theoretical Memory Bandwidth | 460.8GB/s | Approx. 1.6TB/s |
| Interconnect Standard | PCIe 5.0 | PCIe 6.0 generation |
| Power | 400W TDP | Not disclosed |
| Timing | Released June 2023 | Reportedly late 2027 |
The maximum frequency rises from 3.7GHz to 5.15GHz, roughly a 39% increase when comparing top-end figures. Note that this comparison is between maximum-boost-class numbers, not an indication that all cores run at 5.15GHz simultaneously. The 9684X publishes an all-core boost figure of 3.42GHz, but the corresponding figure for the 9006X has not been disclosed. This 39% difference cannot be directly translated into a percentage reduction in simulation time.
The change on the memory side is even larger. The 9684X uses 12-channel DDR5-4800, giving a theoretical bandwidth of 460.8GB/s per socket. The 6th Gen EPYC supports 16 channels and MRDIMMs at speeds up to 12.8GT/s, and AMD lists the 9006X's bandwidth ceiling at approximately 1.6TB/s. Using AMD's rounded figure, that's roughly 3.5x the 9684X's stated theoretical bandwidth.
Calculating 12.8GT/s at 8 bytes per channel across 16 channels yields 1,638.4GB/s, so the 1.6TB/s figure reads as a rounded expression of the platform ceiling. The bandwidth actually available to applications will be lower, depending on memory configuration, NUMA placement, access locality, and internal CPU data paths. Achieving MRDIMM speeds also requires compatible modules and systems, so the published figure alone doesn't determine real-world deployment benefits.
Cache and Bandwidth Cover Two Different Distances
Large L3 capacity and wide memory bandwidth don't serve the same role. 3D V-Cache keeps frequently referenced data close to the CPU, reducing the number of trips needed to fetch from main memory. 16-channel memory increases the volume of data that can be moved at once for data that doesn't fit in cache or for streaming-style read/write patterns. The 9006X is designed to support both the reuse of data placed near the CPU and the supply of distant data, using two separate mechanisms.
Examples where this is likely to show benefits include simulations such as finite element analysis and fluid dynamics, as well as modeling involving iterative computation. Search workloads that traverse large indexes, and analytics that scan data in memory, are also candidates. In workloads that repeatedly read the same matrices, meshes, indexes, or working sets, the higher the proportion that stays resident in L3, the more DRAM accesses can be reduced. Even when the working set greatly exceeds L3 capacity, wide memory bandwidth makes it easier to keep feeding data to the cores.
The fact that AMD includes "large-scale analytics," "retrieval," and "in-memory analytics" among the 9006X's target use cases suggests the company is viewing the scope of HPC more broadly than traditional scientific and technical computing. Search involves traversing large indexes, and in-memory analytics involves repeatedly scanning data resident in main memory. AMD's blog post also cites inference involving long context as a target use case, indicating the 9006X is broadly aimed at workloads with frequent memory access.
Not every workload gets faster with a large cache. For workloads that are compute-bound with little data reuse, that spend time waiting on storage or network I/O, or that hit parallelization limits before anything else, the value of that 1,152MB shrinks. The access latency and operating frequency of the 3D-stacked cache, as well as data movement between chiplets, also can't be inferred from capacity figures alone. Evaluating the 9006X will require benchmarks matched to the data size and access patterns of target applications, rather than composite metrics built from maximum-value figures.
Performance and Operating Conditions That Remain Unknown Until Late 2027
In May 2026, AMD announced the start of production ramp-up for the standard Venice using TSMC's 2nm process. This indicates that manufacturing of the 6th Gen EPYC is heading toward mass production, but it isn't evidence that the 9006X has simultaneously entered the shipping stage. Given the launch timing reported by Tom's Hardware, it should currently be treated as a product plan for the latter half of 2027.
Many figures remain undisclosed by AMD at this time. The 9006X's individual SKU names, pricing, and Default CPU Power are unknown. Base frequency, all-core frequency, and per-model L3 capacity also remain unclear. Supported servers, cloud availability, and maximum memory capacity have not been announced either. While AMD has published comparisons using estimated performance figures for the standard 9006, those results cannot be transposed onto the 9006X. Application performance specific to the 9006X has not yet been published.
What will determine the product's success isn't the eye-catching 1,152MB figure itself, but rather at what power draw, what frequency, and for which applications that capacity can be put to use. The direction is now clear: raise the frequency ceiling and memory supply capability relative to Genoa-X without increasing total L3 capacity. Ahead of the reported late-2027 launch, what remains to be confirmed is which SKUs will be assigned the 5.15GHz clock, how performance and power balance out under all-core load in the 96-core configuration, and how close real-world systems can get to that 1.6TB/s-class bandwidth.