At the OCP Global Summit in San Jose on October 12, AMD CEO Lisa Su held up a physical sample of "Verano," the sixth-generation EPYC processor, during her keynote. Scheduled for 2027, Verano will be the first EPYC with an LPDDR memory interface. Under the plan AMD laid out earlier, it will use low-power LPDDR5X in replaceable SOCAMM2 modules and serve as the host CPU for future Instinct GPUs. Bringing a memory type that matured in mobile devices into servers means balancing power efficiency against part replacement and fault handling.
From plan to hardware on stage
In its OCP announcement, AMD identified the chip Su showed as Verano and reaffirmed its 2027 availability. The LPDDR5X SOCAMM2 plan, first stated in an April 6 memory-technology explainer, has now reached the stage of a physical chip on display. This is not a launch or a shipment of finished servers. The concrete step forward is that the next-generation CPU was shown on stage.
The core count remains uncertain. Wccftech reported up to 192 cores, but said it is unclear whether that figure describes a single chip or a configuration using two 96-core CPUs. AMD's OCP announcement and photo captions contain no specification that settles the breakdown. For now, 192 cores should not be treated as a confirmed per-socket number for comparison with existing products.
To understand Verano's role, it helps to look at what the CPU handles alongside the GPU. At OCP, AMD pointed to agentic AI calling business applications, querying databases and running code. Computation and data movement occur before and after a model generates a response, so raising GPU performance alone still leaves demands on the surrounding CPU and its main memory.
With Verano, AMD is aiming for performance per watt that includes the CPU-side memory. Servers have a fixed power budget, and lower memory consumption widens the room for configuration within the same budget. How much room opens up, however, depends on memory capacity and workload.
Making LPDDR5X memory replaceable
LPDDR5X is a memory technology that delivers high transfer speeds at low voltage. SOCAMM2, meanwhile, is a module format for attaching that memory to servers. Together they combine low power consumption with a way of mounting and replacing the memory.
LPDDR in conventional mobile devices is mostly soldered directly to the board. That suits thin designs, but it limits operations such as removing only a failed memory part or changing capacity later. Servers that are used for years and repaired by swapping components need a different approach.
AMD's memory technology explainer describes SOCAMM2 this way (translated from the Japanese summary of AMD's explanation):
SOCAMM2 modules make it possible to introduce LPDDR5X as a replaceable, serviceable module.
SOCAMM2 modules lie flat relative to the board. AMD says this shape reduces the space the memory takes up inside the server and helps with airflow and the design of liquid-cooling cold plates. The change affects cooling and component layout as well as power.
Memory makers are also preparing. On March 3, Micron announced customer sampling of a 256GB SOCAMM2, up from its earlier 192GB part. This shows that large-capacity, low-power memory is becoming available as modules. Whether Micron's sample will become qualified memory for Verano, and how much capacity Verano can support, must await separate product information.
Separating power savings, replaceability and RAS
While explaining the benefits of LPDDR5X SOCAMM2, AMD also noted that RAS has room for improvement. RAS stands for reliability, availability and serviceability, and concerns how a server keeps running when memory errors or failures occur. Replaceable modules do not by themselves supply all of these capabilities.
LPDDR5X's low power use, SOCAMM2's replaceable structure and server RAS are three separate conditions to check.
| Layer to check | What public explanations confirm | What to verify at deployment |
|---|---|---|
| DRAM electrical characteristics | AMD describes LPDDR5X's low-voltage operation and power efficiency | How total server power changes at the same capacity and workload |
| Module structure | SOCAMM2 can be removed and replaced, and mounts flat | Replacement procedures and cooling design in actual chassis |
| Fault handling | AMD notes a RAS feature gap compared with mature RDIMMs | Features in the final product and the fault tolerance needed on the software side |
This breakdown divides AMD's April 6, 2026 explainer into electrical, form-factor and fault-handling layers, and checks the basis of the power comparison against a footnote in Micron's March 3 announcement. It is not a table of Verano-based performance tests; it is a way to connect each vendor's claims to adoption decisions.
For example, Micron says SOCAMM2 consumes one-third the power of DDR5 RDIMM. The footnote specifies the comparison as between memory modules, not whole servers including CPUs and GPUs. Lower memory power does not guarantee that other components' consumption falls by the same ratio, so the figure cannot be applied directly as a power reduction for Verano systems.
The RAS gap also bears directly on where the technology fits. In its April explainer, AMD said that against the error correction and fault handling RDIMMs have built up over time, LPDDR5X is being strengthened through added chips, memory controllers and software. It also suggested that early uses may be limited to environments where software is highly fault tolerant and does not need all of RDIMM's hardware features.
This does not mean LPDDR5X has no error correction at all. What matters is which errors can be detected and corrected, and at what stage. AMD's explanation is also a technical assessment from April, and should be distinguished from the final RAS feature list of the 2027 Verano servers.
After core counts, implementation conditions matter
The sixth-generation EPYC family is planned to use DDR5 RDIMM and MRDIMM alongside LPDDR5X-based memory. AMD expects DDR memory, with its mature RAS features and supply base, to remain in use for general-purpose computing. Verano looks less like a move to switch every server to the same memory and more like a way to let designers choose according to power and operating conditions.
Capacity and bandwidth also answer different questions. Capacity is how much data can be held at once; bandwidth is how much can be moved per unit of time. Installing large modules does not necessarily make processing faster. The speed of feeding data to the CPU must be considered together with the capacity real applications need. What changes here is the CPU's main memory; it does not replace the memory used by GPUs.
In evaluating 2027 products, system power for a given workload will matter alongside core counts and memory capacity limits. Operators will also want to confirm that hardware fault handling and software recovery capabilities meet the uptime their workloads require. If Verano can secure the needed bandwidth and capacity while supporting fault-time operations, it could be an option for adding compute to AI servers constrained by power limits.