The bottom line: NVIDIA argues that server CPUs built around ever-higher core counts are a poor fit for agentic AI, which needs fast individual threads even under heavy load. Its answer is Vera, which puts 88 Arm cores on a single compute die. That design reduces cross-die communication, but it does not prove that chiplets are inherently slower, and the real-world benefit still has to be verified with actual agent workloads.
In an exclusive interview with Wccftech published October 18, NVIDIA's Vera team said cloud CPUs have sacrificed single-thread performance and IPC (instructions per clock) in pursuit of core density. The concern comes from a new workload pattern: AI agents run inference on GPUs, hand work to the CPU to run tools, then send results back to the GPU. If each CPU step is slow, the agent's entire task takes longer.
Why AI agents need single-thread performance
When an agent writes and tests code, the CPU must build and run the model's output and return the results. If the next decision depends on the previous result, adding cores to run other work in parallel does not shorten the wait. Reducing that sequential latency is why NVIDIA stresses single-thread speed.
At the same time, data centers must run many agents and reinforcement-learning environments at once. NVIDIA's March technical explainer says each environment needs workstation-class single-thread performance, while the system as a whole needs server-class throughput. A CPU that is fast only when few tasks are running, but slows once other cores start consuming memory bandwidth and power, falls short. The metric NVIDIA emphasizes for Vera is per-thread speed with the whole socket under load.
Faster CPUs do not automatically raise GPU utilization, though. If the GPU can run other inference while waiting on the CPU, it stays busy anyway. The benefit depends on the actual workflow and where the waiting time goes.
Vera's key specs and the single-die choice
Vera is a server CPU with 88 custom Arm "Olympus" cores. Its "Spatial Multithreading" runs two hardware threads per core, for up to 176 threads per CPU. NVIDIA's official specifications are summarized below.
| Item | NVIDIA Vera (per CPU) |
|---|---|
| CPU cores | 88 custom Olympus cores (Armv9.2-compatible) |
| Threads | Up to 176 (2 per core) |
| Compute die | 88 cores, shared cache and interconnect on a single die |
| L3 cache | 164MB, shared by all cores |
| Interconnect | Second-generation Scalable Coherency Fabric (SCF) |
| Bisection bandwidth | Up to 3.4TB/s |
| Memory | SOCAMM2 LPDDR5X, up to 1.5TB |
| Memory bandwidth | Up to 1.2TB/s |
| NUMA | One domain per socket |
The key point is that the 88 cores and their interconnect sit on one compute die, while memory and I/O circuitry are on separate adjacent dies. Vera is therefore not a monolithic chip, and it would be inaccurate to say NVIDIA has abandoned chiplet technology altogether.
The 3.4TB/s figure is bisection bandwidth, the data that can cross the boundary when the on-die network is split in two. The 1.2TB/s figure is memory bandwidth. They describe different paths and should not be converted directly into application speed. NVIDIA says Vera sustains over 90% of peak memory bandwidth under load, but that is the company's own measurement and does not guarantee the same result in every application.
How it differs from AMD EPYC
AMD's EPYC 9005 arranges multiple core complex dies (CCDs) around an I/O die. Vera avoids traffic between compute dies by using just one. Based on NVIDIA's explainer and AMD's EPYC 9005 white paper:
| Comparison | NVIDIA Vera | AMD EPYC 9005 |
|---|---|---|
| Core layout | 88 cores on one compute die | Multiple Zen 5 or Zen 5c compute dies |
| Memory/I/O link | Separate adjacent dies | Compute dies connect to an I/O die |
| NUMA as seen by the OS | One domain per socket | Can be configured as one domain per socket (NPS=1) |
NUMA topology and physical die layout are different things. Because EPYC can also present one NUMA domain per socket, the NUMA node count alone does not reveal whether compute is split across dies. What Vera reduces is cross-die communication and the latency variation that comes with it. A single die still has its own latency and bandwidth limits, and memory and I/O contention remain.
Chiplets can still deliver strong single-thread performance
AMD describes Zen 5 as optimized for per-core performance and Zen 5c for density and efficiency, with up to 8 and 16 cores per compute die respectively. Its F-series trades core count for higher clock speeds. So chiplet designs can target either single-thread or parallel throughput. The NVIDIA team's comments challenge the industry's focus on density, but they do not show that chiplets prevent high-performance cores.
IPC is also not determined by die layout alone. Olympus cores can decode up to 10 instructions at once and use advanced branch prediction and out-of-order execution, along with prefetching for graph-like data structures. These are core-level improvements, distinct from reducing inter-die traffic. Even if Vera beats a rival in a given application, the gap cannot be attributed entirely to the single die. Toward the end of the interview, the team itself said it would choose design approaches based on future market needs, rather than rejecting chiplets outright.
Spatial Multithreading: gains and limits
Spatial Multithreading runs two threads per Olympus core, for 176 in total. NVIDIA partitions core resources more explicitly than conventional SMT to reduce contention, for example running main computation and auxiliary I/O work on the same core with less interference. Still, 176 threads is not 176 physical cores. Threads share execution units and caches, so gains vary with the workload.
Phoronix's Michael Larabel tested this in a September 28 review on a dual-socket Vera server (176 cores, 352 threads; Ubuntu 24.04, Linux 6.17 with 64K pages, GCC 15.3). In the results, highly parallel workloads that typically benefit from SMT gained about 20%, with higher power consumption. In OpenFOAM tests on large meshes, however, performance was better with SMT disabled. SMT helps throughput, but not universally, and the tests do not show similar gains in the latency-sensitive step where an agent waits for tool results. NVIDIA's claim of no downside from SMT should be weighed against these independent results.
How to evaluate CPUs for the agentic AI era
Wccftech asked whether CPU-to-GPU ratios could reach 80 to 1. NVIDIA's team did not endorse that figure and said it had no view on a specific ratio. Rising CPU demand from AI is a separate question from predicting a particular ratio. Likewise, NVIDIA's expectation of demand for CPU-only racks does not mean replacing GPUs: GPUs handle training and inference, while CPUs run generated code, manage evaluation environments and prepare input data. The right ratio depends on the workload and wait times, not a fixed number.
To assess Vera, run the same number of agents or evaluation environments on each system and compare total completion time, throughput and power consumption, with matched memory and parallelism. Then determine whether differences come from core speed or from communication and memory efficiency. If waiting on external APIs or storage dominates, a faster CPU helps little; if sequential CPU work is blocking the next GPU inference, speeding it up is worth a lot.
In short, core count and total throughput remain important, but single-thread performance under load and end-to-end latency are becoming key criteria for AI-oriented CPUs. Whether Vera's design delivers an advantage must still be confirmed by comparing real agent workflows on time and power efficiency.