On July 21, 2026, NVIDIA published an architecture white paper for its data center-oriented "Vera CPU." Its custom-designed Arm core, "Olympus," features a 10-wide instruction decoder, a 164MB shared L3 cache, and LPDDR5X memory delivering up to 1.2TB/s. The company also presented estimates showing that, in a 2-socket configuration, it outperformed AMD's EPYC 9755 on the SPECrate 2026 integer test. However, the difference in the overall score is only about 3%, a far cry from the large gap suggested by per-core graphs. Vera prioritizes predictable thread performance and latency under full-socket load for AI agent workloads.
925 vs. 898, Overall Difference of About 3%
According to NVIDIA's white paper, the estimated overall SPECrate 2026_int_base score was 925 for Vera and 898 for EPYC 9755—a difference of roughly 3%. Both systems used a 2-socket configuration with identical optimization flags under GNU 15.2. As a compiler-matched comparison, this is meaningful for gauging Vera's architecture.
| Measurement Condition | NVIDIA Vera | AMD EPYC 9755 |
|---|---|---|
| Physical cores (2 sockets) | 176 | 256 |
| Threads/copies | 352 | 512 |
| Memory | 1.5TB LPDDR5X-9600 | 2.3TB DDR5-6400 |
| SPECrate 2026_int_base (estimated) | 925 | 898 |
Despite having 80 fewer physical cores, Vera slightly edged out EPYC 9755 in overall integer throughput. At least under the specific matched-compiler conditions NVIDIA chose, the combined system—cores, cache, and memory working together—compensated for the core-count disadvantage. Since SPECrate measures work completed per unit time, achieving a higher overall score with fewer cores carries real significance.
However, 925 is not an officially registered SPEC score. Because the Vera system used in testing was a reference system that did not meet SPEC's availability requirements, NVIDIA itself explicitly labels it an "estimate." The company's comparison charts also included values normalized per physical core under load. The white paper's claims of up to 1.9x IPC and up to 2.4x instruction fetch performance operate on a different scale than the socket-wide 925-vs-898 comparison.
It's also worth noting how much results depend on compiler and configuration choices. In SPEC's official database, a Dell PowerEdge M7725 with two of the same EPYC 9755 chips, using AOCC 5.1 with performance-oriented settings, recorded a score of 1070. This is about 16% higher than Vera's 925, though the differing test environments mean it can't be used for a direct head-to-head comparison. If anything, it demonstrates that Vera cannot be generalized as outperforming EPYC processors across the board.
The 10-Wide Olympus Reduces Branch Stalls
Olympus aims to increase the number of instructions processed per clock cycle rather than relying solely on clock frequency. Its front end decodes instructions across a 10-wide width, and multiple branch predictors—including a neural-based approach—can resolve up to two taken branches per cycle. Python runtimes, compilers, and graph analytics commonly used by agents involve heavy branching, and mispredicting the next instruction leaves wide execution units idle. NVIDIA has beefed up prediction and instruction supply to cut down on this idle time.
Caching has also been enlarged to keep single threads from stalling. Each core has a 64KB L1 instruction cache, 96KB L1 data cache, and 2MB of dedicated L2, with all 88 cores sharing a 164MB L3 cache. A graph-oriented prefetcher can look ahead in data structures where the next address depends on the result of the previous read—something ordinary sequential-data prefetching can't handle for pointer-chasing searches and analytics.
The execution units include six 128-bit SVE2 pipelines and support for FP8. The white paper further describes deeper out-of-order execution, allowing independent instructions to proceed while others wait on memory. For its selected workloads, NVIDIA reports up to 2.3x more branch predictions, up to 3.5x more taken-branch throughput, and up to 4.3x more backend throughput compared to EPYC 9755. These are all upper-bound figures from NVIDIA's own measurements and don't imply that entire applications will see the same multiplier in speedup.
Prioritizing Consistent In-Socket Distances Over Core Count
Vera places its 88 cores and shared cache on a single monolithic compute die, with memory and I/O split off into adjacent chiplets. Each socket appears to the OS as a single NUMA domain, so even in a 2-socket configuration there are only two NUMA nodes. NVIDIA explains that by avoiding paths that cross multiple compute dies, it can reduce topology-induced latency variance and inter-die overhead. The white paper does not show a core-density comparison against chiplet-based CPUs, and this claimed benefit also awaits third-party verification under identical workloads.
The Scalable Coherency Fabric supporting the cores offers bandwidth up to 3.4TB/s. Eight memory controllers connect to swappable SOCAMM2 LPDDR5X modules, providing up to 1.5TB of capacity, total bandwidth up to 1.2TB/s, and up to 14GB/s per core. The ability to feed data to every thread even when all 88 cores are fully loaded underpins what NVIDIA calls "single-thread performance under load."
Spatial Multithreading follows the same philosophy. Simply sharing one core's resources between two threads causes one thread's workload to disrupt the other's latency. NVIDIA has designed Olympus's wide resource pool to be more easily partitioned between two threads, yielding 176 threads from 88 cores. The concept envisions pairing a thread demanding maximum performance with a sibling thread handling management tasks. The actual degree of isolation achieved needs to be confirmed through independent workload testing.
Vera's power consumption is configurable in the range of 250–450W. In addition to NVLink-C2C at up to 1.8TB/s, it supports PCIe 6.4 and CXL 3.1. A 2-socket configuration provides 176 PCIe lanes, while the Vera Rubin variant offers 96. This isn't simply a CPU sold on fast cores alone—it's designed to reduce bottlenecks holistically across GPU, memory, and I/O.
Can Performance Claims Be Limited to "AI Agents"?
What Vera's white paper substantiates is a design that handles branch-heavy integer processing and memory-intensive work across the entire socket while keeping core count modest. Because agents wait for the results of tool calls and code execution before proceeding to the next inference step, a delay in any single process holds up the GPU as well. This is precisely why NVIDIA chose to prioritize thread performance consistency and latency under load over raw core density.
On the other hand, the published SPEC overall score is limited to the integer throughput test. There are no results for SPECspeed 2026, which measures single-job performance, or for floating-point workloads, so it's impossible to determine whether Vera holds an advantage in general-purpose server workloads as well. NVIDIA's performance claims of up to 1.9x or 1.8x are also based on its own measurements using selected agent-related workloads.
NVIDIA states that Vera is currently in mass production, with system makers and cloud providers set to begin offering it starting fall 2026. Once official SPEC-registered scores, independently conducted integer tests under matched conditions, and undisclosed floating-point performance data become available, it will be possible to judge whether Olympus's targeted strengths hold up in real product environments as well. Ultimately, Vera's success may hinge less on the number 925 and more on how much it can actually reduce AI agent latency under real-world production workloads.