On January 6, 2024, at a research facility in Hefei, Anhui Province, China, operated by Origin Quantum Computing Technology (本源量子计算科技), the third-generation superconducting quantum computer "Origin Wukong" began operation. More than two years later, in September 2026, Chinese state media outlets including Science and Technology Daily and Global Times reported one after another that a "quantum router" running on this Wukong processor had achieved a transmission efficiency of up to 98%.
The reports were quickly picked up and reprinted by some English-language outlets, framed as a "breakthrough toward large-scale quantum memory." In everyday conversation, the word "router" typically conjures images of communication equipment relaying photons across long-distance fiber-optic networks, or repeaters connecting nodes in a quantum internet. But this experiment was not concerned with inter-city communication infrastructure. It concerns an on-chip component—cooled to near absolute zero inside a dilution refrigerator on a single silicon die—that directs information exchanged between adjacent qubits.
At the core of the announcement is the fact that a building block for constructing bucket-brigade quantum random access memory (QRAM), long considered a theoretical challenge, was operated on real hardware. The published figure of "98%" cannot be taken at face value. There is a structure behind the number that demands careful reading: the transmission efficiency of a single unit, the drop in fidelity when scaling to multiple layers, and the time lag between the paper's publication and its media promotion.
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| Measured value (%) | |
|---|---|
| Single router transmission efficiency | 98 |
| Two-layer network transmission efficiency | 93 |
| Single router fidelity (max paper value) | 95.74 |
| Single router fidelity (reported average) | 94.8 |
| Two-layer network fidelity (average) | 82.4 |
As the chart shows, while single-unit transmission efficiency reaches 98%, the numbers decline progressively when scaling to a two-layer network or when fidelity is measured. Behind the eye-catching figures emphasized by the media, what has the physical system actually achieved, and where does it fall short? Let's start by examining the internal structure of the superconducting chip.
A 10-qubit experimental system handling on-chip traffic control
The superconducting processor "Wukong" is hardware that arranges 72 computational transmon qubits and 126 transmon-type couplers in a grid across the chip. According to Jia Zhilong, of the Chip Research Institute at the Hefei Quantum Computing Engineering Research Center, the total number of physical components, including coupling elements, reaches 198.
In this router demonstration, the team did not operate all 72 computational qubits. Instead, the research team selected 10 transmon qubits from the chip and built a localized experimental system. This is not a demonstration of the entire control infrastructure, but a foundational verification of components using a specific section of the chip.
The experiment's primary focus was confirming the operation of a coherent quantum router (QRouter), the minimal unit of bucket-brigade QRAM. QRAM, like RAM in classical computers, is a mechanism that inputs address information expressed by qubits and reads out superposed data stored in memory while preserving its coherent state. Many quantum computing applications dealing with large-scale data, such as Grover's search algorithm and quantum machine learning (QML), are designed on the premise that this QRAM operates with practical speed and fidelity.
Conventional QRAM designs faced the problem that the number of quantum gates constituting the circuit grows exponentially as the number of address bits increases. Qubits are extremely vulnerable to environmental noise, and the longer the sequence of operations, the more likely decoherence—the breakdown of quantum states—occurs. How to keep circuit depth as shallow as possible while guiding information to the target storage region without loss has long been the central challenge.
The research team—led by first author Sheng Zhang, with corresponding authors Zhao-Yun Chen, Peng Duan, and Guo-Ping Guo—worked in a joint framework spanning the Key Laboratory of Quantum Information at the University of Science and Technology of China (USTC), the CAS Center for Excellence in Quantum Information and Quantum Physics, the Institute of Artificial Intelligence at the Hefei Comprehensive National Science Center, and Origin Quantum. In the paper, the authors claim this is "the first experimental demonstration of coherent quantum routers for bucket-brigade QRAM on a superconducting quantum processor." This is the research team's own claim, not an absolute assessment certified by an independent external body. What was completed was not QRAM itself, but the router components that form the foundation of its wiring technology.
A circuit design that uses the qutrit's extra energy level as an "eraser"
To miniaturize the quantum router and suppress operational errors, the research team employed a technique called the Transition Composite Gate (TCG).
In ordinary quantum computation, only the two levels of a qubit—the ground state and excited state —are used. Attempting to build a router using combinations of standard logic gates based on Clifford groups would require chaining together many two-qubit gates, deepening the circuit and exhausting coherence time.
To address this, the research team temporarily utilized the third energy level inherently possessed by transmons as an intermediary. By leveraging the qutrit property of handling three levels and routing operations through higher-order transitions, they significantly compressed circuit depth compared to conventional gate decomposition.
Specifically, in the control qutrit () carrying address information, the address was encoded in the non-adjacent states and . This design deliberately excludes the intermediate level from address assignment in advance. This arrangement functions as an erasure error (eraser) detection mechanism that automatically flags errors.
The state assignment for the address element is defined as follows: the ground state instructs transfer to the left route, while the second excited state instructs transfer to the right route. The first excited state , positioned between them, is completely excluded from address use and stands by exclusively as an intermediate level for error determination.
After the router operation completes, if the address element is measured in the intermediate state , it can be determined that a leakage or relaxation error occurred during that computation process. In this case, the corresponding data is discarded through post-selection. This is a logical technique that improves fidelity by eliminating unwanted computational results, without adding a physical error-correction qubit.
For coupling between qubits, the team adopted a two-qubit gate. They precisely tuned the qubit and coupler frequencies near the interaction point, optimizing the waveform through experiments using a Floquet excitation sequence.
Furthermore, for single-qubit gates performing address initialization and $X$ flips, they applied DRAG (Derivative Reduction by Adiabatic Gate), a technique for suppressing induced coupling via adiabatic passage. This was to apply high-speed control pulses while suppressing unwanted leakage to higher-order levels.
To confirm that the router maintained a coherent superposition, the research team conducted an interference experiment: scanning the address phase while applying operations in three parallel channels to the input bit , control bit , and the output-destination left bit and right bit . They observed that the occupation probability of the odd excited state traced a clear oscillation pattern as a function of phase , experimentally confirming that information is being distributed while entanglement is preserved.
The difference in meaning between 98% transmission efficiency and 95% fidelity
How was the figure of "98%" that dominated media headlines derived? It's necessary to untangle the definitions of the metrics that reports tend to conflate.
According to the paper, the approximately 98% transmission efficiency for a single router was calculated backward from the residual excitation probability remaining in the input qubit after the routing operation. In the experiment, the residual probability on the input side, , was kept below a threshold of 2.05%. This means that approximately 98% of the input energy was transferred to the output-destination bit.
Meanwhile, as a metric indicating overall system computational accuracy, the authors introduced a benchmark called the Random Access Test (RAT). This is a fidelity metric that measures how accurately the coherence of the input quantum state was preserved.
What must be noted here is that transmission efficiency (the proportion of energy or population transferred) and fidelity (the proportion correctly reproduced, including quantum-mechanical phase information) are entirely different physical quantities. Furthermore, subtle discrepancies exist in the published data between the description in the academic paper and reporting in general media.
| Configuration and Method | Transmission Efficiency | Random Access Fidelity (RAT) | Basis and Nature of Metric | Source |
|---|---|---|---|---|
| Single router (with erasure error suppression) | ~98% | Max 95.74% | Input bit residual probability . Fidelity is the best value from paper abstract | Zhang et al. (arXiv:2505.13958) |
| Single router (state media report) | Up to 98% | Average 94.8% | Appears to be the average of measurements across 3 independent routers | Global Times, People's Daily Online |
| Two-layer network (with erasure error suppression) | 93% | Average 82.40% (fitted value) | Measured value at depth $N=0$ is 90.02%. Declines with increasing depth | Zhang et al. (arXiv:2505.13958) |
| Two-layer network (without erasure error suppression) | Not disclosed | Average 81.90% (fitted value) | Measured value at depth $N=0$ is 78.50%. Raw data without post-selection applied | Zhang et al. (arXiv:2505.13958) |
The abstract and conclusion of the academic paper list a maximum fidelity of "95.74%" for a single router. Meanwhile, Global Times and People's Daily Online, along with Interesting Engineering which cited them, reported an "average fidelity of 94.8%." This 94.8% figure is thought to represent the average across three independent router units fabricated for the experiment.
The decline in performance becomes pronounced when the network is scaled to multiple layers. When a two-layer quantum routing network was constructed, overall transmission efficiency dropped from 98% for a single unit to 93%. Random access fidelity fell even further, from around 95% for a single unit to an average of 82.40% across two layers.
A comparison based on whether erasure error detection was applied is also important. At routing depth $N=0$, the measured fidelity with erasure error suppression (post-selection of the intermediate level ) applied was 90.02%, whereas without the suppression mechanism it stood at only 78.50%. Even in the fitted average fidelity, the value with suppression was 82.40% compared to 81.90% without. While eliminating erasure errors confirmed a roughly 11-point boost, this advantage diminishes as the network deepens.
The authors themselves cite two-photon transitions in the address element, imperfect gate operations, and temporal decay of data information as reasons for the stepwise degradation in performance with increasing routing depth. Level leakage caused by decoherence and microwave control is the largest contributor to infidelity, and this gives rise to asymmetry between the left and right output paths and, occasionally, misrouting of data. The figure of 98% is merely a snapshot of energy-transfer efficiency captured under the most favorable conditions for a single unit.
The "five-layer" wall imposed by chip-plane geometry
Beyond the performance degradation associated with multi-layering, the paper explicitly states a more fundamental physical constraint: the upper limit on placement across the processor plane, i.e., a ceiling on scalability.
The research team developed a layout algorithm for efficiently arranging numerous routers on the superconducting chip. This method starts from a reference triangle (seed triangle) and iteratively grows triangular links toward topologically advantageous regions. It comprehensively evaluates each qubit's coherence time, crosstalk between components, and hardware wiring constraints to search for optimal placement.
Assuming the Wukong processor's grid topology, the optimal arrangement places the seed triangle near the center of the processor and expands components outward in a quasi-circular fashion. This maximizes packing efficiency.
However, even with this optimization, the paper acknowledges that the current chip structure can only accommodate a system of "up to five layers."
Attempting to expand the network beyond five layers makes physical overlap between quantum routers unavoidable on the two-dimensional plane. Since this is planar wiring, avoiding crossovers would require introducing additional technologies such as short-distance transmission techniques connecting remote bits on the chip, or three-dimensional stacked wiring.
The challenges the authors list for the future are not limited to router placement overlap. They also include intensifying crosstalk accompanying increased component density, and cumulative transmission errors that build up through multi-stage relaying. As solutions, the research team cites further refinement of post-selection techniques, introduction of high-coherence component fabrication processes, and fine-tuning of control waveforms. But these are pathways presented as future prospects, not achievements demonstrated in this experiment. It would be premature to conclude that experimental results using a mere 10 out of 72 bits have opened the path to large-scale QRAM.
The backdrop to a media blitz arriving 15 months after paper publication
There is one more element that should not be overlooked when evaluating this announcement: the time lag between the preprint's publication and the media coverage.
The paper detailing the technical specifics of this research, "Demonstrating Coherent Quantum Routers for Bucket-Brigade Quantum Random Access Memory on a Superconducting Processor," was registered on the preprint server arXiv on May 20, 2025 (arXiv:2505.13958). This matches records in academic databases such as INSPIRE.
Overseas specialist media outlet The Qubit Report and others report that the research was published in the peer-reviewed journal Physical Review X, Volume 16 (paper number 031051), dated August 25, 2026. The Anhui Provincial Key Laboratory of Quantum Computing Chips explained the research to Science and Technology Daily on September 2, 2026, following which Origin Quantum issued a press release, and Global Times reported on it on September 3.
The wave of "98% quantum router" reporting that suddenly erupted in September 2026 was not the result of newly obtained experimental results, but rather a product of the publicity cycle triggered by the journal publication.
It should also be noted that the source of the reporting is the very company that participated in the research. Origin Quantum is both a co-author organization of the paper and the source of the press release that supplied information to the media. Promotional phrases like "fast lane for data transmission" are not objective technical terminology, but rhetorical flourishes originating from the corporate release.
The fact that the work passed peer review as an academic paper does underpin its technical soundness. However, downstream benefits discussed in the reporting—"cost reduction," "leaps in computational efficiency," "integration of chip and circuit design"—are inferences made by the researchers that go beyond the experimental data itself.
The vast gap between implementation technology and commercial QRAM
Sober analysis of this experimental achievement has also come from experts within China. Tian Feng, former head of the Intelligent Industry Research Institute at SenseTime, offered the following caution in an interview with Global Times:
"Achieving 98% transmission efficiency does not mean that large-scale QRAM has immediately entered the stage of commercialization."
Tian Feng cited the continuing difficulty of error control and long-term hardware stability as the biggest barriers to practical implementation. He also pointed out that quantum computer performance should not be evaluated simply by the number of qubits alone. His analysis suggests that the essence of this achievement lies not in blindly increasing physical bits, but in cleverly utilizing the qutrit's extra energy level to boost the operational efficiency of limited hardware resources.
As technology outlets such as PC Central have also pointed out, the system developed here remains a laboratory-stage prototype, and neither a commercialization timeline nor pricing has been specified.
Competition in quantum computer development is shifting away from a stage focused on how many qubits can be packed onto a chip, and toward an architectural competition over how to practically implement on-chip interconnects and memory hierarchies. The experiment by Origin Quantum and collaborators demonstrates the possibility of reducing wiring depth while detecting errors, by leveraging multi-level control of superconducting circuits.
But when the network is expanded from two to three layers, and ultimately to the five layers considered the physical limit, how much of the fidelity—already dropped to the low-80% range—can be sustained? Can three-dimensional component arrangements be realized beyond the limits of planar stacking? The question of achieving practical quantum memory remains unresolved.