The Information reported on July 20, 2026, that Google is developing a server chip called "Frozen v2," which fixes part of Gemini's model architecture directly into hardware. According to the plan, the number of AI tokens processed per unit of power consumption would increase 6 to 10 times compared to Google's latest custom AI chip, with deployment possible as early as 2028. However, Google has not announced the product, and the amount of model information to be embedded in the circuitry has not been finalized. Given that Google already has TPUs for inference, why would it need another chip lineage that's nearly dedicated to Gemini alone? The answer lies in the tension between TPUs, which retain flexibility, and a design that hardwires model-specific information into the circuit.
A Gemini-Specific Circuit Aiming for 6-10x
According to The Information's report, Frozen v2 directly incorporates elements of Gemini into its circuitry to boost inference-time efficiency. The comparison metric is the number of AI tokens that can be processed per watt. Therefore, the "6 to 10 times" figure does not mean response speed increases by the same multiple. No product benchmark has yet been published that holds power and throughput constant while measuring latency and model quality under the same conditions.
Throughput per watt affects supply capacity just as much as the number of chips that can be housed in a data center. In its official announcement of the 8th-generation TPU, Google explained that power is currently the constraint on its data centers. The company stated that the amount of compute its data centers can supply per unit of power has increased sixfold over the past five years. If Frozen v2's target is achieved, Google could deliver more Gemini responses from its existing power budget.
The design has not yet been finalized. While Google is reportedly planning to introduce the chip as early as 2028, engineers are still working out how much model information to hardwire. Expanding the scope of what's fixed makes it easier to boost efficiency by eliminating general-purpose processing. On the other hand, if future versions of Gemini adopt a different architecture, the mismatch with the fixed circuitry would grow larger.
A Google Cloud spokesperson told Reuters that the company's teams continuously research and experiment with new technologies, co-designing hardware and software from the ground up to integrate and optimize systems. This statement reflects Google's design philosophy but does not officially confirm the name, performance, or launch timeline of Frozen v2. At this point, the 6-10x figure should be treated as a development target rather than a confirmed outcome.
Narrower Than TPU 8i, Going Deeper Into Model Architecture
Google's 8th-generation TPU is split into TPU 8t for training and TPU 8i for inference. TPU 8i features 288GB of high-bandwidth memory and 384MB of on-chip SRAM, tripling SRAM capacity compared to the previous generation. Inter-chip bandwidth for Mixture of Experts (MoE) models has also doubled to 19.2Tb/s, and a dedicated engine handling collective operations reduces on-chip latency by up to fivefold. This is a design aimed at cutting the time processors spend waiting for data during inference.
Even so, TPU 8i remains capable of running a wide variety of workloads. In addition to JAX and PyTorch, Google natively supports major software such as SGLang and vLLM, and offers these to cloud customers as well. The ability to swap in different models or inference engines is precisely what gives TPUs their value as a computing platform.
Frozen v2 moves in the direction of narrowing this flexibility further. If, as reported, Gemini-specific architecture is shifted into the circuitry itself, it could reduce some of the repeated computation and data movement that occurs during execution. In exchange, however, the freedom to run different models on the same circuit diminishes. If Google's official description of TPU co-design amounts to a "model-aware general-purpose accelerator," then Frozen v2 is an attempt to move closer to an "inference circuit tailored to a specific model."
In its official materials, Google states that the 8th-generation TPU offers up to 2x the performance-per-watt of its predecessor, Ironwood, and that TPU 8i delivers 80% better performance-per-price compared to the prior generation. Frozen v2's 6-10x figure is a different metric altogether, and even the specific chip model used as the baseline cannot be confirmed from publicly available information. Simply lining up these numbers side by side does not support the conclusion that Frozen v2 outperforms TPU 8i by an equivalent multiple.
The Cost of Efficiency: Keeping Pace With Model Updates
Chip development cycles are longer than AI model update cycles. Google itself acknowledged in its 8th-generation TPU announcement that bringing hardware to market takes several years, requiring the company to design ahead of future technology and demand. If Frozen v2 is to run in 2028, the circuitry being decided now must remain compatible with whatever version of Gemini exists at that time.
A design that hardwires model architecture creates a collision between two different timelines. Silicon cannot be substantially changed after manufacturing, but Gemini continues to be updated as software. If the fixed portions remain usable for a long time, more inference can be extracted from the same power and data center infrastructure. Conversely, if Gemini's architecture changes, Google will face a choice: adapt the new model to fit the existing chip, forgo the efficiency gains, or wait for the next chip generation.
This constraint is consistent with reports that Frozen v2 will not replace TPUs. If TPUs continue to handle a broad range of models, training, and external customer workloads, while only sufficiently stable, high-volume Gemini inference is shifted to the Frozen line, Google could avoid sacrificing flexibility across its overall operations. This approach would also align with the goal of easing compute resource constraints. That said, Google has not disclosed the target workloads, production scale, or whether the chip will be offered externally.
The Deployment Decision Hinges on Fixed Scope and Measured Results
Evaluating Frozen v2 first requires specifications on exactly what gets hardwired into the circuit. A description as vague as "elements of Gemini" does not reveal which computations and data movements can be eliminated, or how much room remains for model updates. Once the fixed scope is known, the compatibility traded away for the 6-10x efficiency gain can also be measured.
What's needed next is power-per-token data measured under identical model quality and latency conditions. An inference chip that increases throughput but slows response times, or loses efficiency in low-utilization scenarios, cannot achieve the intended reduction in overall service costs. Whether the design targets can be reproduced in an actual data center depends not on the chip alone, but on the entire system—memory, networking, and cooling combined.
Finally, the division of labor with TPUs will determine the business significance of this chip. If Google can limit Frozen v2 to stable, high-volume Gemini inference, it can redirect TPUs toward external customers and newer models, increasing the total AI processing capacity supplied from the same infrastructure. If, by 2028, the fixed scope and comparison conditions are disclosed, and efficiency is confirmed to hold even after Gemini's architecture is updated, Frozen v2 will represent a new tier of model-specific silicon integrated into large-scale services.