Information has surfaced that development of Google's next-generation AI chip, the TPU v9, which involves MediaTek, is running behind schedule. On October 19, 2026, Taiwan's Commercial Times (工商時報) reported that design changes have pushed tape-out to January 2027, and that shipments could come in January–March 2028. However, neither Google nor MediaTek has officially announced a delay. The report highlights that in custom AI chip development, what matters is not only the design of the compute circuitry itself but also the ability to integrate memory and high-speed interconnects and turn them into a product that can be manufactured reliably at volume.
Design changes ripple into surrounding circuits; shipments reportedly in early 2028
According to the Commercial Times article of October 19, the TPU v9, reportedly code-named "Humufish," has seen development slip by about three weeks because of design changes to Core A, and the effects have extended to the design of Core B and the I/O circuitry, which are said to be MediaTek's responsibility. These details are based on information from institutional investor sources, not an official development schedule published by Google or MediaTek.
The paper says the target of submitting samples in November 2026 is being maintained, while the first tape-out is slated for January 2027 and the finalization of the production design for the second quarter of that year. Tape-out refers to finalizing a semiconductor's circuit design and handing it over to the manufacturing process. Even once a design is finalized, however, a chip cannot be mass-produced and shipped immediately; it must go through prototyping, verification, and manufacturing process adjustments.
The report does not explain what the samples due in November actually are. It is therefore not possible to conclude that they are finished TPU v9 prototypes, or to treat them as the same stage as the January 2027 tape-out. Nor does the early-2028 shipment outlook necessarily mean the start of service on Google Cloud, since shipping chips and making them available to customers in the cloud are separate stages.
It is also unclear how much the roughly three-week design delay will affect the final shipment date. The original official shipment target is not given, so this information alone does not allow one to say how many months the schedule has slipped. Still, it suggests that as multiple design blocks are integrated, a change in one area can spread to surrounding circuits and affect the schedule of the whole product.
MediaTek's role goes beyond compute circuitry
In a technical explainer published on June 24, MediaTek described custom ASICs for data centers as combining compute dies with memory interface circuits and high-speed I/O. A die is an individual semiconductor chip cut from a wafer. The company says it aims not only to integrate these into a single package but also to optimize performance and power efficiency with the entire rack in view.
An ASIC (Application-Specific Integrated Circuit) is a dedicated semiconductor designed for a particular purpose. In AI ASICs, adding more compute units to raise computing power does little good if memory cannot supply data fast enough; the compute units end up waiting for data to arrive. When processing is spread across multiple dies, high-speed links are also needed so the dies can exchange large volumes of data. For that reason, the design must cover not just the compute circuitry but also memory connections, die-to-die communication, and power delivery as a whole.
Given this structure, there is a technically understandable background to the report that a design change in Core A led to revisions in Core B and the I/O circuitry. Because different circuits operate together within the same package, design dependencies such as data handoffs and interfaces remain even when different teams are responsible for them. That said, which circuits or interface specifications were changed has not been disclosed, so the specific cause of the delay cannot be identified.
Note also that MediaTek's explainer describes its custom ASIC business in general and is not a document revealing the internal configuration of the TPU v9. The claim that MediaTek handles Core B and the I/O circuitry likewise rests solely on the Commercial Times report. Even so, it shows that in AI ASIC development, it is increasingly important not just to take on compute circuit design but to combine memory and interconnect technologies into a system customers can actually use.
Google's current TPUs are designed differently for training and inference
On April 22, 2026, Google announced two eighth-generation TPUs: the "TPU 8t," aimed mainly at large-scale pre-training, and the "TPU 8i," optimized for running AI models and inference. Google's published technical specifications show that even within the same generation, compute performance, memory capacity, and chip-to-chip interconnect differ depending on the use.
| Google's published specs | TPU 8t | TPU 8i |
|---|---|---|
| On-chip SRAM | 128MB | 384MB |
| HBM capacity | 216GB | 288GB |
| Peak FP4 compute | 12.6PFLOPS | 10.1PFLOPS |
| Chip-to-chip interconnect | 3D torus | Boardfly |
Particularly notable is that the inference-oriented TPU 8i has more on-chip memory than the training-oriented TPU 8t. The TPU 8i's SRAM capacity is 384MB, three times the TPU 8t's 128MB. Meanwhile, peak FP4 performance is 12.6PFLOPS for the TPU 8t and 10.1PFLOPS for the TPU 8i, so the training model leads in maximum compute.
However, triple the SRAM does not mean triple the real-world processing speed. FP4 is a metric for peak 4-bit floating-point performance and cannot be used to directly compare processing times for different workloads. Google has optimized the TPU 8i's on-chip memory capacity and communication scheme for inference. In other words, a chip with higher raw compute is not necessarily better at every AI task.
How Google's official product lines correspond to the TPU v9 code name and development partners in this report has not been made clear. Nor can the purpose or internal configuration of the next-generation TPU v9 be judged from its generation name alone. Still, the fact that Google already designs different TPUs for different uses shows that competition in custom AI chips depends not only on compute power but also on whether a company can design memory configurations and chip-to-chip connections suited to the target workload.
Intel's EMIB-T reportedly used for TPU v9; substrate yield is the key to volume production
There is also a new projection about the advanced packaging technology for the TPU v9. In the summary of its independent research published on October 13, TrendForce predicted that the TPU v9 will adopt Intel's advanced packaging technology "EMIB-T." It also expressed the view that package substrate yield in 2027 will determine the ramp-up of volume production and cost competitiveness. However, neither Google nor Intel has officially announced the adoption of EMIB-T, and the published summary gives no specific yield figures.
According to Intel's technical materials, EMIB (Embedded Multi-die Interconnect Bridge) is a technology that embeds small silicon bridges in the package substrate to connect adjacent dies at high speed. Rather than placing a large silicon interposer across the entire package, it places bridges only where die-to-die connections are needed. EMIB-T adds through-silicon vias (TSVs) to this, also enabling vertical power delivery to HBM.
In this kind of advanced packaging, the package is not merely a container to protect the semiconductors. It plays a vital role in connecting multiple dies at high speed, transferring large amounts of data to and from memory, and supplying power to each circuit. However high-performing the compute circuitry, if it cannot be assembled into a product that works properly together with memory and interconnect circuits, it will not become computing power customers can use.
What matters here is manufacturing yield, the proportion of manufactured products that are usable as good units. If the defect rate at the substrate manufacturing stage is high, more substrates must be produced to secure the required number of good units, raising costs. Moreover, manufacturing the substrate itself differs from the assembly process of mounting multiple dies on it, so it is necessary to distinguish which stage's yield is being referred to. Substrate yield alone cannot tell us the production efficiency or cost of the finished package as a whole.
Intel says it has used the earlier EMIB in volume production since 2017. But that track record does not guarantee the yield or manufacturability of the EMIB-T reportedly intended for the TPU v9. If the adoption of EMIB-T turns out to be true, a new supplier could join advanced AI chip packaging, but whether it can supply stably at a competitive cost is a separate question. What matters is not the name of the technology but whether enough good units can be produced continuously with it.
MediaTek's ASIC expansion goals and the TPU v9 schedule should be considered separately
In an official blog post on September 22, MediaTek said it expects revenue from its AI data center ASIC business to exceed $2 billion in 2026. It also forecast that the custom AI ASIC market will reach $80 billion in 2027 and set a goal of capturing 15–20% of that market opportunity, raised from the 10–15% target it had stated as of June. This suggests the company positions its custom ASIC business as a growth area amid the expanding AI data center market.
However, these are forecasts and targets for MediaTek's overall ASIC business, not a revenue outlook for the TPU v9 alone. Also, because the year for which the market size is forecast and the timing for achieving the market share target do not necessarily coincide, one cannot make a definitive estimate of 2027 revenue by multiplying $80 billion by 15–20%. Likewise, it would be premature to conclude that reports of TPU v9 development delays will affect MediaTek's entire 2026 revenue outlook. The custom ASIC business may include multiple projects, and the timing of volume production and revenue recognition differs for each product.
In Taiwan's ASIC industry, some companies are already posting sharp sales growth. GUC (Global Unichip Corporation) reported September 2026 revenue on October 5 of NT$7.145 billion, up 97.8% from a year earlier. However, because this monthly sales release gives no breakdown by customer or product, it is impossible to judge how much Google's TPU demand contributed.
Going forward, in assessing the TPU v9's development, what will matter is not only when the design changes are completed but also how far volume-production readiness advances for the packaging technology adopted. If MediaTek properly integrates the compute circuitry, I/O and other designs, and manufacturers can supply products at sufficient yield, Google will find it easier to scale up deployment of purpose-built AI chips. Conversely, if a problem arises in any stage, product shipments and actual service rollout could be affected even if the design itself is complete. To expand in the custom ASIC market, companies need not only to win development projects but also to establish a system that moves smoothly from design to volume production and supplies stably at the scale customers require.