At a technical briefing on September 3, 2026, KIOXIA disclosed performance simulation results for its "KIOXIA XL1 Series," a Compute Express Link (CXL)-compatible memory expansion module built on its low-latency "XL-FLASH" technology. According to EE Times Japan, replacing one-third of DRAM with XL1 kept performance degradation under 5%, and at the same cost, the company achieved double the capacity and 1.3 times the performance. However, the product itself was already announced on August 3, and there is no confirmation that the evaluation samples—originally slated to ship that same month—have actually shipped. What's new here isn't the product's existence, but rather the numbers showing how well a design that places NAND beneath DRAM can preserve performance.
Samples Planned for August Are Still "Coming Soon" in September
Plans for the KIOXIA XL1 Series have been taking shape incrementally for at least a year. In its June 2025 business strategy materials, KIOXIA outlined plans to ship samples of CXL-connected XL-FLASH in the second half of 2026. On August 3, 2026, the company formally named the product XL1 and announced it would be shown as a reference exhibit at FMS 2026. Evaluation samples for industry partners were slated to ship "within August."
Yet EE Times Japan's coverage of the September 3 briefing described sample shipments as "coming soon." It's unclear whether the August timeline shifted, or whether shipping preparations were actually complete and only the wording differs. As of September 7, KIOXIA's official website shows no update announcing completed shipments. While this timeline doesn't definitively prove a delay, it's clear the product has not yet advanced to mass production.
Moreover, the August announcement included a caveat: some functions of the evaluation samples remain untested, and specifications may change. Capacity, form factor, supported CXL generation, and bandwidth have not been disclosed. Power consumption, pricing, mass production timing, and customer names also remain unknown. What increased at the September briefing wasn't product specifications—it was the results of internal simulations.
The Conditions for Replacing a Third of DRAM
XL1's goal isn't to replace DRAM entirely with NAND. At the briefing, Katsuki Matsudera explained that 80% of memory accesses concentrate on just the top 20% of overall data. Frequently accessed data stays in DRAM, while the rest moves to XL1. By matching media to access frequency, expensive DRAM can be concentrated on data that genuinely requires speed.
The speed gap between media types is substantial. In a hierarchy diagram KIOXIA presented in 2025, DRAM read latency was under 40 nanoseconds, XL-FLASH sat at 3–5 microseconds, and typical TLC NAND was under 40 microseconds. XL-FLASH is faster than conventional NAND, but it doesn't match DRAM speeds. While CXL builds on PCIe to provide a pathway allowing hosts to read and write to connected devices as memory, it doesn't eliminate the underlying media's latency.
KIOXIA pairs XL-FLASH—which takes over 100 microseconds for write and erase operations—with a dedicated controller, claiming this reduces latency by more than 90% compared to a "conventional method." The absolute latency figure for that comparison baseline wasn't disclosed. Similarly, the results showing under 5% performance degradation when replacing a third of DRAM, and double capacity with 1.3x performance at equal cost, come from internal simulations without disclosed server configurations, applications, or datasets.
Therefore, the 5% figure isn't proof that XL1 delivers near-DRAM performance across every AI workload. Rather, it supports a design hypothesis: under conditions where low-frequency data is correctly identified and access to slower media is minimized, reducing DRAM capacity can have a limited impact on overall performance. What's needed next is verification that the same trend holds up on customers' actual hardware and real-world workloads.
CXL, Storage-Next, and CMX Are Separate Pathways
The three products KIOXIA is simultaneously advancing can easily blur together under a simple description like "using flash as memory." XL1, GP1, and CM10 all belong to the same NAND strategy, but they serve distinct layers: CXL-based CPU memory expansion, high-speed SSDs read directly by GPUs, and SSDs for CMX's KV cache.
| Product/Configuration | Connection & Media | Primary Role | Public Status as of September 7, 2026 |
|---|---|---|---|
| KIOXIA XL1 Series | CXL, XL-FLASH | Places low-frequency data in CPU-side memory space | Evaluation samples planned for shipment within August; completion unconfirmed |
| KIOXIA GP1 Series | PCIe 6.0 / NVMe 2.2, 2nd-gen XL-FLASH | High-speed flash directly read by GPUs, supplementing HBM | Evaluation samples planned for select customers by year-end |
| KIOXIA CM10 Series | PCIe 6.0 / NVMe 2.1, 10th-gen BiCS FLASH TLC | Places KV cache on large-capacity SSD via CMX | Sample shipments to select customers began as of July 30 |
| NVIDIA CMX (Context Memory Storage) | BlueField-4, NVMe SSD, Spectrum-X | Builds a shared KV cache tier at the pod level, outside the GPU | Configuration presented for NVIDIA Rubin |
XL1 is accessed as memory from the CPU via CXL. GP1, meanwhile, is an SSD boasting up to 10 million random read IOPS at 512-byte granularity and up to 50 DWPD, aiming for direct GPU access in line with NVIDIA's Storage-Next. CM10 is also an SSD, but this one packs up to 61.44TB of TLC NAND and targets CMX's large-capacity KV cache tier, where BlueField-4 manages NVMe SSDs.
In other words, the relationship between XL1 and NVIDIA—emphasized by TrendForce—shouldn't be interpreted as joint development around a single CXL product. While KIOXIA has stated that CM10 supports CMX, NVIDIA's official CMX webpage doesn't list KIOXIA as an individual partner. What can be confirmed from public materials is that KIOXIA has prepared SSDs supporting two separate NVIDIA initiatives, while also developing XL1, a CXL module for CPUs, as a distinct effort outside those two.
Why KIOXIA Isn't Directly Replacing DRAM
HBM and DRAM, which handle the fastest tier in AI servers, offer far lower latency than NAND. KIOXIA's strategy isn't to seize that fastest tier, but rather to shift infrequently used data to lower tiers, making the most of limited HBM and DRAM. XL-FLASH fills the gap between DRAM and ordinary TLC NAND, TLC NAND handles capacity and bandwidth, and QLC NAND takes on even larger storage capacity.
This isn't classification for the sake of expanding the product lineup. In AI inference handling long contexts, the KV cache—storing past computation results—balloons in size. In retrieval-augmented generation, the vector databases GPUs reference also grow large. Loading everything onto HBM or DRAM would be fast, but capacity and cost become constraints. So data gets distributed across XL1, GP1, and CM10 based on reuse frequency and required latency.
On the business side, KIOXIA views this tiering strategy as its next growth area after smartphones and PCs. In June 2026, the company set a mid-to-long-term target of raising the revenue share from data centers and enterprise to over 60%. It plans roughly ¥470 billion in annual capital expenditure and about ¥230 billion in annual R&D spending over the next three years. The return on this investment doesn't hinge on XL1's success alone, but on how many NAND-based tiers can be added within AI server architectures.
Software, Not Capacity, Will Determine Adoption
A memory hierarchy isn't a system that automatically gets cheaper just by plugging in slower media. Get the timing wrong—keeping the wrong data in DRAM or moving it to XL1 at the wrong moment—and microsecond-scale latencies will pile up, dragging down performance. This is why KIOXIA highlighted, at FMS 2026, technology extending Linux's DAMON (Data Access Monitor) mechanism to improve tiered management of CXL-connected flash.
Durability also shapes suitable use cases. The briefing cited an endurance rating of over 150,000 write cycles for XL-FLASH, and GP1 claims up to 50 DWPD, but XL1's capacity and warranty terms haven't yet been released. Beyond that, operational design distinct from DRAM will be needed—covering write concentration avoidance, data protection during failures, and behavior after server restarts.
The real basis for evaluating XL1 isn't flashy capacity multipliers, but the actual shipment date of evaluation samples and the data placement methods used on real hardware. Power consumption, durability, pricing, and mass production timing are equally essential. If these are disclosed and the sub-5% performance degradation can be reproduced across multiple customer environments, NAND will be positioned to move decisively from a storage device into a genuine tier within the AI server memory hierarchy.