On October 21, 2026, Micron published a development roadmap for AI-oriented memory and storage technologies, including DDR6, which targets more than double the memory bandwidth of DDR5, and "G11," a next-generation NAND flash memory with more than 400 layers. The roadmap also covers low-power LPDDR6 and "vHBM," which stacks memory on top of compute chips, and the company plans to improve technologies across the whole path, from data storage capacity to transfer routes to the processors. However, the bandwidth expansion and power reduction figures are targets for different technical challenges and do not directly indicate improvements in overall system performance. A joint explainer with Meta on LPDDR6, released the same day, also reveals a design approach that prioritizes effective bandwidth and power efficiency in AI servers, not just higher peak transfer speeds.
DDR6 targets more than 2x bandwidth, with 1TB RDIMMs in view
Micron's next-generation DRAM, DDR6, is intended for server applications that demand high reliability. LPDDR6, meanwhile, targets data centers and mobile devices, aiming to cut power consumption compared with the previous generation. For server memory modules, Micron also showed technology that enables a 1TB RDIMM (Registered DIMM). However, this indicates a technically achievable capacity, and no specific product launch has been decided.
Based on pages 19 and 23 of the technical presentation that Micron published on October 21, the performance targets and comparison baselines for each technology are summarized below.
| Technology / Product | Announced performance / specs | Comparison baseline | What the figure represents |
|---|---|---|---|
| DDR6 | More than 2x memory bandwidth | DDR5 | Performance improvement target |
| LPDDR6 | Over 35% lower power consumption | LPDDR5 | Power efficiency improvement target |
| High-capacity RDIMM | 1TB memory capacity | A capacity figure in itself | Technical capability, not a commitment to productization |
| G11 NAND | About 2x bit density, up to 1.5x I/O speed | G9 NAND | Performance target on the development roadmap |
| G11 NAND | Over 25% lower data transfer energy per bit | G9 NAND | An efficiency metric for data transfer, distinct from total SSD power consumption |
These figures show the improvements each technology aims for; they are not performance comparisons between products measured under the same conditions. The DDR6 and LPDDR6 improvement rates carry notes indicating that they are targets. Even if DDR6 more than doubles memory bandwidth, overall AI processing will not speed up by the same factor, and the LPDDR6 power improvement of over 35% cannot be taken as the reduction in total server power consumption.
On higher memory capacity, Micron began sampling 512GB DDR5 RDIMMs in September 2026, supporting speeds of up to 9,200MT/s. The newly announced 1TB RDIMM is a technical goal looking beyond that. However, the presentation gives no specific launch date and explicitly states that it does not guarantee productization.
On manufacturing, Micron plans to begin expanding volume production of its next-generation DRAM process, "1δ (1-delta)," in the second half of 2027. It aims to improve bit density by the mid-20% range over the current 1γ (1-gamma), and plans to use it for next-generation LPDDR and DDR as well as HBM5 and vHBM. However, the 1δ volume ramp timing is a manufacturing process plan and does not mean all related memory products will launch at the same time.
How LPDDR6 aims to improve bandwidth and power in AI servers
A technical explainer on LPDDR6 co-authored by Micron and Meta engineers addresses the challenges of memory capacity and power consumption in AI inference. Running a large AI model requires holding not only the model parameters but also data such as the KV cache generated during inference. The KV cache stores information computed while processing past context so it can be reused in later processing. The longer the context a model handles, the more storage capacity is needed, and the more important it becomes to read and write that data efficiently.
LPDDR6 splits a 24-bit-wide channel into two independently operating 12-bit subchannels. This aims to process multiple memory access requests in parallel and raise the bandwidth actually available. In addition, in the server-oriented "x6 mode," the data width per memory die is narrowed so that more dies can be packed into a package. The design is meant to increase memory capacity within limited board area.
However, narrowing the data width is not merely a way to add capacity. The joint explainer also describes a mechanism in which the memory controller coordinates access across multiple subchannels, handling the transfer of a block of logical data with fewer commands than accessing them individually. The aim is to reduce the burden of issuing large numbers of fine-grained access requests and to allocate bandwidth and power more efficiently to actual data transfer. Therefore, the narrower per-die data width in x6 mode should not be equated with a simple drop in overall server memory bandwidth. Actual performance also depends on how the memory controller manages multiple dies and subchannels.
Mechanisms for reducing power consumption are also strengthened. LPDDR6 uses separated power rails and DVFS (Dynamic Voltage and Frequency Scaling), which adjusts voltage and operating frequency according to load. According to the joint explainer, unlike LPDDR5X, data transfer can continue even while voltage is being switched. It also has a mechanism that reduces the activity of one subchannel when high bandwidth is not needed, cutting the power consumed by I/O signal switching.
AI server workloads are not constant, and the memory bandwidth required varies with the state of inference processing. It is therefore important not only to raise peak transfer speed but also to see how far power consumption can be cut under low load. What Micron and Meta emphasize is, in addition to peak bandwidth, steadily using the bandwidth actually needed for real inference while reducing wasted power.
Server use also demands reliability for long, continuous operation. In addition to error correction inside the memory die, LPDDR6 supports periodic memory checks and error detection through command and address signal parity. The explainer also describes a mechanism that monitors how many times a row has been opened, as a countermeasure to "Rowhammer," where repeated access to the same memory row corrupts neighboring data.
However, in-die error correction alone cannot complete data protection for the whole system. The joint explainer shows a design that limits the impact of memory failures to a confined area and combines this with advanced error correction on the SoC side. In other words, adopting LPDDR6 in AI servers requires securing performance, power consumption and reliability across the entire system, including the memory controller and SoC, not just the specifications of the memory chip itself.
vHBM stacks on compute chips; G11 NAND goes beyond 400 layers
"vHBM," shown in Micron's roadmap, is a concept that stacks memory on top of a compute chip. Ordinary HBM is placed next to a compute chip such as a GPU and secures wide connection bandwidth. With custom HBM, functions co-designed with the customer are built into the memory's base die. vHBM changes the connection structure itself further, aiming to shorten the distance between memory and processor by stacking memory on top of it.
However, stacking memory on a compute chip requires balancing high-density connections with heat dissipation. Micron's presentation cites hybrid bonding, which connects chips with fine contacts, and technology that lowers thermal resistance to spread heat efficiently. It also shows configurations that combine conventional HBM with vHBM, suggesting that different packaging approaches may be used side by side depending on the application. Even with shorter connection distances, expected performance cannot be maintained unless the heat generated by the processor and memory is handled properly. Putting vHBM to practical use will therefore require both higher connection density and sound thermal design.
The same roadmap includes "vEIM," aimed at on-device AI inference. Targets for the first-generation product were given as 2TB/s of memory bandwidth and energy consumption of less than 1pJ per bit. These performance values and development schedules are listed as targets that may change. Likewise for vHBM, its appearance on the roadmap cannot be interpreted as confirming a specific launch date or product specifications.
In storage, Micron presented a development plan for "G11," next-generation NAND flash with more than 400 layers. G11 uses wafer-bonding technology, and volume production is scheduled to expand from the second half of 2027. Compared with the current G9 NAND, it aims to raise bit density by about 2x and I/O speed by up to 1.5x. Bit density here is a metric of how much data can be recorded in a given area; it does not mean that SSDs using G11 will necessarily have twice the capacity or half the price.
For G11, Micron also sets a goal of reducing the energy needed for data transfer by more than 25% per bit. The approach is not only to raise storage density by adding NAND layers but also to improve efficiency when reading and writing stored data. For technologies after G11, Micron is considering materials with high charge mobility and higher-density memory cell structures. Beyond expanding capacity, improving the efficiency of data transfer paths is the direction of future NAND development.
Micron also presented different product concepts for AI NAND depending on access characteristics. The high-IOPS type is SLC NAND aimed at efficiently handling small-unit data access originating from GPUs, prioritizing the number of input/output operations that can be processed per unit time. The high-bandwidth type, by contrast, is a concept that stacks NAND using TSVs (Through-Silicon Vias, electrodes that pass through silicon) and a logic base die, placing large-capacity storage near the processor. The former emphasizes responding to many fine-grained access requests, the latter large-volume data transfer, and both envision uses different from conventional SSDs that simply increase storage capacity.
Getting the most from AI requires optimizing the whole memory hierarchy
Micron's presentation lays out a division of roles: HBM feeds data to the processor at high speed, main memory such as DDR and LPDDR holds working data, and SSDs and NAND store large volumes of data and in-process context. The joint explainer with Meta on LPDDR6 also positions LPDDR6 as memory that complements DDR and HBM according to use, rather than replacing them. What this roadmap shows is a direction not of consolidating all data into a single fast memory but of using multiple memory technologies according to capacity, bandwidth, power consumption and how data is accessed.
Given this division of roles, evaluating next-generation memory will depend on different metrics for each. For LPDDR6, the question is how far power consumption can be cut at low load while sustaining the bandwidth real AI inference needs. For vHBM, the focus is whether the heat and dissipation challenges can be solved while exploiting the benefit of a shorter connection to the processor. For NAND, the suitable design differs depending on whether the goal is to improve frequent access to small data or to transfer large volumes of data quickly.
What ultimately matters is not the peak performance of individual memory chips but how much lower latency and power an actual AI system needs to sustain the same workload. In long-term operation, memory error detection and correction and recovery from failures must also be evaluated. If the next-generation technologies Micron is promoting meet these conditions, they could draw more efficient performance out of processors and raise the throughput of AI services as a whole. Going forward, besides the volume production ramp of G11 NAND and 1δ DRAM scheduled for the second half of 2027, verifying the performance and power consumption of DDR6, LPDDR6, vHBM and others when built into real systems will be important.