
HW/SW Co-design on FPGA That Physically Halts Unnecessary Computation via "Commands"
A hardware/software co-design accepted to MICRO 2026 uses the signal of "which task is currently being executed" in a multi-task inference model to physically skip unnecessary compute tiles on an FPGA. It cuts FLOPs by up to 76% and shortens latency by 2.4x, while the contrast with the same mask causing a 22% slowdown on GPUs clearly reveals the hardware requirements for exploiting sparsity.








