US semiconductor giant Qualcomm announced on September 2, 2026, a new generation of graphics architecture called "Adreno Neural Fusion," which will power its next-generation mobile platforms. The architecture places a dedicated AI compute core—the "Adreno Matrix Cores," running at 1.45GHz—inside each of three GPU slices, paired with an ultra-low-latency, GPU-adjacent cache called "Adreno HPM (High Performance Memory)" totaling 18MB. Together, these components establish a unified graphics pipeline that integrates neural processing, AI super-resolution, and frame generation.
The rendering demands of mobile gaming have grown steadily year after year, forcing an ongoing trade-off between high-fidelity graphics, high frame rates, and smartphone battery life. How can manufacturers reduce rendering load and power consumption while suppressing the flickering of fine details and ghosting artifacts that conventional spatial and temporal upscaling techniques struggled to avoid? Qualcomm's answer wasn't to offload AI processing to an NPU, but rather a physical architectural overhaul: embedding matrix multiplication units directly into the GPU's rendering pipeline and keeping all data circulation within on-chip caches.
Why Matrix Cores Needed to Live Inside the GPU, Not the NPU
Until now, AI processing on mobile SoCs has largely been the domain of a separate NPU (such as the Hexagon NPU). However, leveraging an NPU for real-time 3D graphics rendering runs into insurmountable bandwidth and latency barriers.
In game rendering running at 60fps or 120fps, transferring intermediate buffers, G-buffers, and tile data rendered by the GPU to the NPU via the system bus (NoC), and then sending inference results back to the GPU, consumes an enormous amount of system DRAM (LPDDR) bandwidth. DRAM access is the single largest power draw in mobile SoCs, and in smartphones where thermal design power (TDP) is constrained to just a few watts, increased memory round-trips lead to fatal heat buildup and battery drain.
Qualcomm's approach was to integrate AI-dedicated compute units directly within the GPU pipeline—the "Adreno Matrix Cores." The new-generation Adreno GPU features three independent slices, each containing a dedicated Matrix Core running at 1.45GHz.
This allows neural network inference to be invoked directly within the same pipeline context as vertex shading, rasterization, and pixel shading. Because data never leaves the GPU subsystem, the latency penalty associated with memory round-trips is minimized, enabling immediate processing within the rendering cycle itself.
How the 18MB HPM Cache Cuts DRAM Round-Trips and Delivers 40% Power Savings
Even with high-speed AI compute units built into the GPU, the pipeline stalls if data supply lags behind. To eliminate this bottleneck, Qualcomm introduced a new 18MB GPU-dedicated cache: "Adreno High Performance Memory (HPM)."
Smartphone GPUs use Tile-Based Deferred Rendering (TBDR), which divides the screen into small rectangular regions for rendering. Adreno HPM's role is to keep all of this tile-based rendering data, intermediate frame buffers, and the compute workloads demanded by AI models entirely within nearby on-chip memory.
In conventional GPU architectures, intermediate frames were frequently written out to and read back from main memory during resolution upscaling and post-processing effects. The 18MB HPM absorbs all of this on-chip, dramatically reducing the frequency of external LPDDR access. By keeping intermediate data circulating within the chip through the three-slice proximity memory design, bus congestion is avoided and frame rate drops are suppressed.
The synergy between the Matrix Cores and HPM delivers up to 40% better power efficiency when the feature is enabled. In smartphone form factors where thermal throttling from heat buildup is unavoidable, a 40% reduction in power consumption translates directly into more stable frame rates and extended battery life.
Overcoming Shimmering and Ghosting: A Break From Traditional Spatial and Temporal Interpolation
Qualcomm has previously offered rendering-assist technologies such as "Snapdragon Game Super Resolution (SGSR)" and "Adreno Frame Motion Engine (AFME)." However, these were primarily algorithms built on general-purpose shaders, not deep learning inference run on dedicated AI silicon.
As a result, conventional upscaling carried specific weaknesses: severe flickering of fine details such as thin wires or grid patterns—known as "shimmering"—trailing outline artifacts left behind fast-moving characters or camera movements, known as "ghosting," and an overall softening of image clarity compared to native resolution. Players had no choice but to accept these visual compromises in exchange for higher frame rates.
Adreno Neural Fusion fuses neural processing, AI super-resolution, and frame generation into a single pipeline. By having a trained model jointly infer geometric information and temporal vectors, the system improves the precision of edge interpolation and significantly suppresses artifacts caused by motion prediction. Qualcomm is essentially attempting to replicate, within mobile's TBDR architecture, the same kind of technological leap that NVIDIA's DLSS achieved on PC graphics when it moved beyond spatial interpolation with the power of Tensor Cores.
Unity and Unreal Engine Support From Day One, and Matrix Units Now Span the Entire Platform
The biggest hurdle determining whether a graphics technology succeeds or fails is the barrier to real-world adoption by game studios. Technologies that demand vendor-specific proprietary APIs or complex shader code tend to be avoided due to development cost concerns.
On this front, Qualcomm has built standard, Day 1 integration of the Adreno Neural Fusion stack into both of the two dominant commercial game engines, "Unity" and "Unreal Engine." Studios can enable the switch within their existing game development workflows and reap the benefits of high-quality super-resolution and frame generation, without having to build their own custom implementation pipeline.
With the introduction of Adreno Matrix Cores, matrix compute units are now present across Qualcomm's entire lineup of major processors. The company previously announced the "second-generation Oryon CPU," which raised clock speeds to 5GHz, along with "FlexCache," a restructured cache hierarchy—meaning that matrix acceleration units are now embedded in all three of its core engines: the NPU (Hexagon), the CPU (Oryon), and the GPU (Adreno).
Rather than relying on a single processor, the groundwork is now in place for distributed computing that routes AI workloads to whichever silicon best matches the nature of the task. At the "Snapdragon Summit 2026," scheduled to take place in Hawaii starting September 22, Qualcomm is expected to unveil full details of its next-generation flagship SoC built around Adreno Neural Fusion, along with real benchmark results and live demos of supported game titles.