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Explore English articles about AI Semiconductor.
Cerebras' CS-4 keeps the same 5nm wafer but redesigns power delivery, cooling, and I/O to double peak compute per wafer. Here's what the performance claims actually cover and how production-ready the system really is.
Xiaomi's second-generation SoC, the XRING O3, stays on 3nm while expanding to 10 high-performance CPU cores, a 16-core GPU, LPDDR6, and a 200TOPS NPU. This article separates official figures from measurements on a development board to examine what the 113.8GB/s memory bandwidth and 20W-class peak power actually mean.
d-Matrix's Raptor accelerator measured roughly 105 TB/s of card-level bandwidth using 3D-DRAM in real silicon. But its inference speedups come from architectural modeling, not third-party benchmarks, and production yield data remains unpublished.
During peak summer, when annual sunlight is at its strongest, solar panel efficiency can actually decline. This article explains the physical property known as the "temperature coefficient," which causes output to drop by 0.4–0.5% for every degree above the 25°C baseline, the specific voltage-drop mechanism behind it, and why manufacturers' 25°C standard differs from real-world operating conditions.
Facing memory shortages and rising costs, Apple is exploring chip procurement from Chinese suppliers, drawing fierce pushback from the US Congress over security concerns. The issue has grown beyond corporate strategy, becoming a potential bargaining chip in diplomatic negotiations tied to an upcoming US-China summit.
Edgewater Research has suggested a multi-year memory contract between NVIDIA and Micron. While the companies' mass-production relationship and Micron's anonymous strategic customer agreements are already public, the contract's duration, volume, and pricing remain unconfirmed.
Rapidus has published a roadmap to build an 8-reticle (6,640 mm²) interposer on a 600×600mm glass panel by 2030. Claiming more than 12 times the yield efficiency of a 300mm wafer, the company is pursuing a manufacturing approach distinct from TSMC's wafer-based route to scale up AI chips.
As AI chip TDPs exceed 1 kW and liquid-cooling adoption jumps from 6% to 53% in three years, thermal management has replaced raw performance as the top constraint in semiconductor design. From imec's STCO research to Samsung's zHBM concept and KAIST's AI design agents, here's a look at the front lines of the battle against heat.
LG Electronics PRI has reportedly received its first order for a semiconductor packaging LDI tool from an unnamed OSAT. Confirming mass-production adoption still requires details on throughput, overlay accuracy, and yield after delivery.
CXMT will account for 11.3% of the world's net DRAM bit supply growth in 2026, but Hanwha forecasts that shortages will continue through 2027 even after the production increase. Here's how to read the denominators and supply constraints behind the numbers.
