TSMC has signaled that it may support customers who adopt a competitor's advanced packaging technology if that supply falls short. On the company's October 15, 2026 earnings call, Chairman and CEO C.C. Wei stressed that TSMC is producing large packages equal to five times the reticle area in volume, with good yields. Asked what would happen if customers using Intel's "EMIB-T" could not get enough supply, he said the top priority is helping customers bring their products to market smoothly. TSMC also acknowledged, however, that its own back-end capacity, including advanced packaging, is tight. For AI chipmakers, whether TSMC can actually serve as an alternative supplier depends not only on how mature its volume-production technology is, but also on redesigning products for a different packaging approach and securing production capacity. Wei's remarks on the earnings call show a willingness to support customers, but they do not guarantee actual supply capacity.
TSMC's "5x" and Intel's "more than 9x" Cannot Be Compared Directly
At its technology symposium on April 22, 2026, TSMC announced that it was already producing CoWoS at 5.5 times the reticle area. The "5x" Wei mentioned on the earnings call should therefore not be read as a newly achieved scale-up. What was emphasized this time is that TSMC is manufacturing for actual customer products in volume and maintaining good yields. The multiples are expressed differently in the April announcement and the October remarks, but that alone does not indicate a different technology generation or a step backward in performance.
A reticle is the master plate used in the exposure step of semiconductor manufacturing to transfer circuit patterns. The reticle multiple generally expresses area in terms of a single exposure field. When comparing large packages, though, what the area is measured against matters. The area of the interposer that handles chip-to-chip wiring, the total silicon area of the compute chips and memory mounted on the package, and the outer dimensions of the finished package are all different metrics.
Intel is also scaling up its advanced packages. In its ECTC 2026 technical report, published June 2, the company said it demonstrated a configuration using EMIB-T in which the combined silicon area of compute chips and memory exceeds nine times the reticle area. It also said the package's outer dimensions were extended to as much as 120 × 120 mm. However, this is a technology demonstration reported at a conference; it does not show that customer products with the same specifications can be mass-produced at high yields.
| Technology / disclosure | What the figure represents | Confirmed development / production stage |
|---|---|---|
| TSMC's 5.5x CoWoS | Scale of the area integrated with CoWoS | Announced as in production as of April 2026 |
| Intel EMIB-T's 9x+ | Combined silicon area of mounted compute chips and memory | Technical demonstration reported at ECTC 2026 |
| Intel EMIB-T's 120 × 120 mm | Outer dimensions of the package | Demonstrated in the same technical report |
While TSMC's CoWoS technical materials give the reticle multiple of the interposer, Intel's "more than 9x" refers to the total area of mounted silicon. Comparing the two companies' published figures as-is does not tell you which packaging technology is superior. Nor does Intel's demonstration reveal volume-production yields for customer products, and TSMC's implied claim that only it can mass-produce at 5x scale does not prove that no other company has large-package technology. Evaluating competitiveness requires comparing production track record, yields, and cost under the same conditions, in addition to how area is defined.
Using CoWoS as an Alternative Requires Design Changes and Validation
TSMC's "CoWoS-L" and Intel's "EMIB-T" share the approach of placing fine silicon interconnects only where needed to connect multiple chips at high density. CoWoS-L combines an interposer built on a redistribution layer (RDL) with local silicon interconnects (LSI). Its structure differs from CoWoS-S, which connects a wide area using a large silicon interposer, and CoWoS-L packages at 3.5 times the reticle size have been in volume production since 2024. This structure allows flexible placement of large compute chips and high-bandwidth memory (HBM).
Intel's EMIB technology, meanwhile, uses small silicon bridges embedded in the substrate to connect adjacent chips at high density. EMIB-T adds through-silicon vias (TSVs) to these bridges, using vertical connections to improve power delivery. CoWoS-L and EMIB-T are both technologies for integrating compute chips and HBM into a single package, but their wiring layouts and power delivery structures are not identical.
For that reason, moving a product designed for EMIB-T to CoWoS-L is not simply a matter of switching the company that manufactures it. Chip-to-chip connections, power supply, and internal package wiring must be adapted to the destination approach, and electrical operation and reliability must be validated. The extent of the changes varies by product design, however, and the compute chip itself does not necessarily have to be redesigned. If a product is designed in advance to support multiple packaging approaches, the burden of switching suppliers may be reduced.
Testing also needs attention on the way to volume production. Intel separates its testing into screening of chips before they are assembled into a package, final testing after assembly, and system-level testing that checks operation under conditions close to real use. For products carrying many expensive compute chips and HBM stacks, it is important to distinguish the yield at intermediate assembly stages from the proportion of finished products that operate to specification. When comparing yields across companies, one must also confirm which product and which process step a given figure covers.
The question on the earnings call about whether TSMC could serve as an alternative supplier if Intel's capacity falls short came from a Morgan Stanley analyst. Wei avoided a direct answer but said the top priority is enabling customers' products to reach the market smoothly, indicating a positive stance toward helping. He did not, however, announce a plan to move specific customer products from EMIB-T to CoWoS or a dedicated production allocation for that purpose. Even if a customer prepares a CoWoS-ready design, whether TSMC can produce the required volume when needed remains a separate issue.
$2 Billion Deal with GlobalFoundries, With Supply Expansion Starting in 2028
One concrete step TSMC is taking to increase advanced packaging capacity is its partnership with GlobalFoundries (GF). On October 8, 2026, GF announced a $2 billion agreement to manufacture silicon interposers in the United States for TSMC's CoWoS. The initial term is five years, and GF will expand production capacity at its manufacturing site in Malta, New York. The aim is to strengthen the supply of CoWoS components in response to rising demand for AI and high-performance computing (HPC) chips.
What GF handles under this agreement is the manufacture of silicon interposers, which carry the wiring between chips. It is not an announcement that the entire CoWoS package assembly process is being transferred to GF. TSMC is working not only to increase its own manufacturing capacity but also to expand its back-end supply chain by using outside companies. However, GF's additional capacity is scheduled to come online in the first half of 2028, so it will not immediately resolve the supply shortage as of 2026.
Separately, at its April 22 technology symposium, TSMC announced that it will begin producing CoWoS at 14 times the reticle scale in 2028. The technology is said to integrate roughly 10 large compute dies and 20 HBM stacks in a single package. The two companies' announced future plans are as follows.
| Subject | Planned production start | Plan details |
|---|---|---|
| TSMC's 14x CoWoS | 2028 | Large-package technology able to integrate about 10 large compute dies and 20 HBM stacks |
| GF's U.S.-made silicon interposers | Volume ramp begins in 1H 2028 | Expanded capacity to make silicon interposers supporting the CoWoS supply chain |
The 14x CoWoS information is based on the April 22 official announcement, and the GF start timing on the October 8 announcement. Both are future plans, and it has not been announced that interposers made by GF will be supplied exclusively for 14x CoWoS. The fact that the two companies' plans overlap in 2028 also does not mean TSMC currently has spare capacity sufficient to make up for a competitor's supply shortfall.
After 14x CoWoS production begins, TSMC also plans to expand beyond 14x in 2029. If larger packages allow more compute chips and HBM to be mounted, the production capacity required at each stage, from component procurement to assembly and testing, grows as well. Even if individual steps achieve high yields, it does not follow that all necessary components can be gathered and finished products supplied reliably. The GF agreement shows that, alongside developing technology for larger packages, the capacity to supply the components that support manufacturing must also be secured.
Whether TSMC's Support Materializes Depends on Customer Product Volumes and Supply Capacity
On the earnings call, Wei also explained that TSMC is developing "CoPoS," an advanced packaging technology that uses panels, with the aim of reducing costs in the future. At the same time, he stressed that for now CoWoS is customers' first choice. While advancing technology development for future large packages, TSMC is also working to strengthen its ability to reliably mass-produce and ship current customer products.
TSMC itself, however, acknowledges a supply shortage in back-end processes, including advanced packaging. On the call, it positioned the GF partnership as part of its strategy to expand back-end capacity and said it wants to secure the supply customers need in both front-end and back-end processes. In other words, even if TSMC is willing to help a competitor's customers, it does not necessarily have sufficient production capacity for that purpose at present.
To judge whether TSMC could actually become an alternative supplier for EMIB-T, one would need to confirm when the relevant products begin volume production, their yields, and whether the required quantities can be supplied. For Intel as well, the track record of conventional EMIB in volume production, the EMIB-T technology demonstration, and volume production of individual products using EMIB-T should be evaluated separately. Likewise, TSMC's explanation that it produces 5x-reticle-scale packages with good yields alone does not reveal how much additional orders from new customers it could accommodate.
To limit supply-shortage risk, AI chipmakers need to consider multiple packaging approaches early in product development and proceed with the necessary design, validation, and securing of production slots. The support stance TSMC has shown may widen customers' options for suppliers, but actual alternative production requires preparation on both the technology and capacity fronts. The key questions going forward are how far TSMC can expand volume production of large CoWoS, and whether customers who adopt competing technologies can build systems that let them switch suppliers when needed.