Shrinking chip circuits does not depend solely on shortening the wavelength of the light used for exposure. In China, where procurement of extreme ultraviolet (EUV) lithography tools with a 13.5nm wavelength is restricted, manufacturers are pushing ahead with advanced chips by combining 193nm deep ultraviolet (DUV) immersion lithography tools with multiple patterning. Analysis of a processor in a commercially available smartphone has confirmed that scaling can proceed without EUV.
But being able to manufacture a chip technically is a separate question from producing it reliably in volume at a competitive price. To form fine circuits with DUV, whose wavelength is far longer than EUV's, a complex pattern must be split up and processes such as exposure and etching repeated. That increases how often masks and manufacturing equipment are used, and it raises the risk of defects at each step as well as the time needed to make a chip. What China's semiconductor industry faces is not only the technical challenge of forming fine circuits, but also the economic barrier of turning that into a profitable manufacturing process.
How 193nm Immersion Lithography and Multiple Patterning Complicate Manufacturing
Chipmakers have long combined two approaches to scaling: shortening the exposure wavelength to improve resolution, and splitting circuit patterns across multiple process steps while using existing exposure technology. According to a technical explanation of its 1-alpha (1α) generation DRAM published by Micron Technology (Micron), the argon fluoride (ArF) excimer laser used in conventional immersion lithography has a wavelength of 193nm, while EUV tools use 13.5nm. In general, the shorter the wavelength, the easier it is to form fine patterns, although actual resolution also depends on the optics and process technology.
Multiple patterning evolved as a way to use 193nm light to produce circuits too fine to form with a normal single exposure. The technique splits a complex, fine circuit pattern into two or more simpler patterns and forms the final circuit through multiple processing steps. Specifically, it repeats exposure, development and etching, and, depending on the method, forms sidewall spacers to create patterns finer than the exposure tool's resolution limit. Micron's explanation likewise says that achieving the 1-alpha generation required a combination of computational lithography, immersion exposure, double patterning, repeated patterning and high-precision overlay technology.
With EUV, circuit layers that would need multiple patterning passes with DUV can sometimes be formed in fewer steps. With DUV multiple patterning, by contrast, the first exposure, development and etching are followed by the formation of additional patterns, with further deposition and etching as needed. Advanced alignment control is also essential to overlay the multiple patterns accurately. The added steps not only create more opportunities for defects, but also affect how long equipment is occupied and how long it takes to finish a single wafer.
Even if multiple patterning can form fine circuits, that alone does not make commercial volume production viable. A chip that works properly in a prototype or limited product does not necessarily come with sufficient per-wafer yield or throughput, meaning processing capacity per unit of time. Manufacturing cost per good die, characteristics such as power consumption and operating frequency, and physical dimension differences relative to competitors' same-generation processes must also be verified separately.
How Far Did SMIC's "N+3" in the Kirin 9030 Scale?
Reverse-engineering analysis of commercial products is an important clue for judging how far China's leading foundry, SMIC (Semiconductor Manufacturing International Corporation), has advanced miniaturization. Semiconductor analysis firm TechInsights disassembled and analyzed the Kirin 9030 processor in Huawei's Mate 80 Pro Max smartphone and identified it as being made on a process called SMIC's "N+3." The company's analysis showed that SMIC has further scaled its existing manufacturing technology and applied it to an actual commercial processor.
However, TechInsights does not assess N+3 as having reached the level of TSMC's or Samsung Electronics' (Samsung) established 5nm processes. Rather, it positions it as a further development of the 7nm-class technology SMIC developed earlier. In its comparison of physical dimensions, N+3's circuit density also falls short of TSMC's and Samsung's commercial 5nm processes, indicating a difference in the degree of scaling.
One caveat is that SMIC itself has not published a product plan using the names "N+3" or "5nm" in an official roadmap. The N+3 label should be treated as a technical classification based on analysis by third parties such as TechInsights. In addition, detailed comparison data, such as gate density and circuit structure dimensions, is available only to subscribers of TechInsights' paid platform. As a result, it is not possible to state precisely, from publicly available information alone, by what percentage circuit density differs from TSMC's and Samsung's 5nm processes.
Overlay Errors and Larger Die Area Push Up Production Costs
The major challenge with DUV multiple patterning is not only whether fine circuits can be physically formed, but whether the manufacturing method can be sustained economically. Chris Mack, co-founder and chief technology officer (CTO) of semiconductor metrology and lithography company Fractilia, described in an interview with Tom's Hardware Premium a rule of thumb about exposure costs that was once shared across the industry. According to it, three exposures with 193nm immersion tools and one exposure with an EUV tool were generally considered to cost about the same.
But if four 193nm masks are needed to replace one EUV exposure, the cost balance breaks down and EUV becomes clearly cheaper, he said. Of course, this is a rule of thumb based on past equipment operation and not a formula that applies as-is to every fab today. Actual costs vary with equipment acquisition prices, utilization rates, mask costs, process configuration and other factors. Even so, it shows that the more times patterning is split, the more disadvantaged DUV tends to become on manufacturing cost.
Multiple patterning also makes it harder to manage "overlay," the accurate alignment of circuit patterns formed in different steps. The more times exposure and etching are repeated, the more tightly positional shifts and processing variations at each step must be controlled, and inadequate control can lead to fatal defects such as shorts or open circuits in wiring. To prevent such defects, designers might build in margin in wiring spacing and similar features at the design stage, but that would lower circuit integration and could enlarge the die area of the finished processor.
What determines the profitability of chip manufacturing is not only how many wafers can be processed but how many sellable good dies are ultimately obtained. A larger die area reduces the total number of dies that can be cut from a wafer of the same size. If lower yield from manufacturing defects is added on top, the number of saleable dies per wafer falls further. In addition, if repeated exposure and etching lengthen the manufacturing cycle, equipment throughput is also affected. However, no verifiable public data has been released on SMIC's specific yields, wafer prices or fab utilization, making it difficult to compare actual manufacturing costs quantitatively.
DUV vs. EUV: Manufacturing Technology and Demonstrated Results
In advanced chip manufacturing, different technical and economic choices have been made around DUV multiple patterning and the adoption of EUV. Comparing SMIC's logic chip with Micron's DRAM helps clarify how the potential and limits of DUV show up.
| Process / Chip | Exposure technology and basis | Confirmed results | Remaining challenges / constraints |
|---|---|---|---|
| SMIC N+3 (Kirin 9030) | Multiple patterning with immersion DUV. Reverse-engineering analysis of a commercial product | Scaling confirmed as a development of SMIC's 7nm class | Falls short of TSMC's and Samsung's 5nm processes in circuit density; volume yield and wafer cost are undisclosed |
| Micron 1-alpha (DRAM) | Immersion DUV and multiple patterning without EUV. Official technical documents | Achieved volume production of the leading-edge DRAM process of its time without EUV | Success with regular memory circuits cannot be applied directly to complex logic circuits, and there are limits to further scaling |
| Micron 1-gamma (DRAM) | Manufacturing technology combining EUV and immersion DUV. Official technical documents | Claims more than 30% higher bit density per wafer than 1-beta | New materials and design changes also contributed in addition to EUV, so EUV's effect alone cannot be separated out |
Note: The improvement of more than 30% for Micron's 1-gamma is the company's own published figure, and the absolute values for the baseline and the comparison target are not given in the public materials we were able to confirm. Also, because circuit structures and evaluation metrics differ between DRAM and logic chips, this table cannot be used to compare their manufacturing difficulty or economics directly.
What Micron's DRAM Shows About DUV's Potential, and How Logic Chips Differ
Micron's DRAM development is an important past example in answering how far chip scaling can go without EUV. For its 1-alpha generation DRAM, the company chose to thoroughly optimize 193nm immersion lithography without adopting EUV. At the time, while Samsung and SK hynix were moving ahead with EUV, Micron achieved volume production of leading-edge DRAM without it by combining computational lithography, multiple patterning and high-precision process control. The case shows that existing DUV technology can achieve advanced scaling, and that commercial production can continue if appropriate design and manufacturing processes are combined.
However, Micron did not maintain a strategy of scaling with DUV alone. For its subsequent "1-gamma (1γ)" generation, the company introduced EUV exposure and adopted next-generation high-k metal-gate (HKMG) CMOS technology. According to Micron's official announcement, the 1-gamma generation improved bit density per wafer by more than 30% compared with the previous 1-beta. But this figure reflects improvements to the process as a whole and not the effect of introducing EUV alone. Because it also includes refinements to transistor structure, materials, design and other manufacturing steps, EUV's standalone contribution to the density gain has not been disclosed.
What matters here is the difference in circuit structure between DRAM and leading-edge logic chips. As Fractilia's Chris Mack points out, DRAM memory cell areas have a structure in which regular patterns repeat, making it relatively easy to advance "Design-Technology Co-Optimization (DTCO)," which jointly optimizes circuit design and manufacturing technology. Logic processors used in smartphones, PCs and similar devices, on the other hand, combine circuits with various functions and complex wiring, with diverse pattern shapes and layouts. As a result, even with the same multiple patterning, handling overlay accuracy and design constraints can be more complicated. The fact that Micron succeeded in volume production of an advanced process using DUV for DRAM does not mean the same economics and yields can be reproduced for leading-edge logic chips.
Dutch Export Controls and the Economic Barrier at 3nm and 2nm
Export controls on lithography tools are also an important constraint in considering China's advanced chip manufacturing. However, the Dutch government's rules do not uniformly ban exports of all DUV lithography tools. According to an official statement from lithography giant ASML, from September 1, 2023, the Dutch government required export licenses for the immersion DUV system "TWINSCAN NXT:2000i" and later leading-edge immersion lithography systems. Whether a license is granted is reviewed on a case-by-case basis. At the time of that statement, sales of EUV lithography tools were already restricted, while ASML's other equipment was not covered by the regulation.
In a September 6, 2024 announcement, ASML further explained that authority to issue export licenses for the immersion DUV systems "TWINSCAN NXT:1970i" and "NXT:1980i" would be transferred from the U.S. government to the Dutch government. The change took effect the following day, September 7. In other words, while the range of controlled equipment and the body reviewing export licenses have changed in stages, not all DUV tools have become subject to a total embargo on shipments to China. Which equipment Chinese chipmakers can procure depends on the models concerned and the outcome of export license reviews.
In this procurement environment, China's semiconductor industry faces not only technical limits on forming fine circuits but also the question of whether a balance between manufacturing cost and performance can be achieved. Chris Mack has expressed the view that making next-generation logic chips such as 3nm and 2nm commercially viable without access to EUV would be extremely difficult. In theory, splitting patterning many more times might make it possible to form still finer circuits. But if the required number of masks and the exposure and etching steps increase and manufacturing times lengthen, costs rise sharply. If lower yields are added on top, then even if chips can be made, keeping prices competitive in the market becomes difficult.
To push scaling without EUV, Chinese chipmakers must raise precision and yield while accepting more complex manufacturing processes and a heavier equipment burden. Widening circuit design margins could increase die area, and adding equipment to make up for throughput would raise the investment burden accordingly. However, because SMIC's actual yields and manufacturing costs are not public, it is not possible to judge objectively how profitable the current technology is.
Analysis of commercial products has confirmed that leading-edge logic chips can be scaled without EUV. But that does not mean the process has achieved circuit density or manufacturing costs equal to those of competing processes that use EUV. Going forward, besides the Dutch government's review of export licenses for immersion DUV tools, how far SMIC can improve yield and production efficiency will be important. In judging the competitiveness of China's chip manufacturing technology, the question is not only what nanometer-equivalent chips can be produced, but how many good chips can be supplied stably from a single wafer, and at what cost.