On October 14, 2026 (U.S. time), IBM and Siemens announced a research collaboration to advance design and manufacturing technology for the "nanostack," an architecture that stacks transistors in three dimensions. The work combines the 0.7nm-generation structure IBM showed in June with Siemens' expertise in electronic design automation (EDA) and manufacturing simulation.
The day before, on October 13, IBM also disclosed plans to offer a research process design kit (PDK) in January–March 2027. The move marks a step from demonstrating that stacked devices work to building circuits from them and estimating the effects of wiring and heat. The collaboration shows what challenges remain in turning the nanostack into a technology designers can actually use.
What will the Siemens collaboration make it possible to design?
The two companies are developing design, simulation and lithography technologies for the current 7-angstrom (0.7nm) node and generations beyond it. According to IBM's announcement, they will build virtual models of the nanostack, estimate performance and optimize designs before chips are made, and examine manufacturing issues. Siemens brings its EDA tools along with expertise in manufacturing process simulation and exposure optimization.
With a three-dimensional layout, calculating only the transistors drawn in a circuit diagram is not enough to predict real behavior. Wiring has resistance that impedes current flow, and neighboring wires and devices create capacitance that stores charge. Extracting these unintended electrical effects from the actual layout and building them into simulation is known as parasitic resistance and capacitance extraction.
In a September 30 explainer on CFETs, which stack n-type and p-type devices vertically, Siemens cites electrical coupling between overlapping gates, between source and drain regions, and through the insulating materials between layers. Models must account not only for devices side by side but also for the relationship between those above and below. IBM's PDK explainer likewise lists heat flow and the interaction between upper and lower devices as new items to examine, in addition to resistance and capacitance.
In other words, there is a gap between being able to place more devices and being able to draw out circuit performance from that arrangement, and design models have to close it. If wiring delay and thermal effects can be estimated, designers can try layout changes and send the results back to the manufacturing side. The research can be read as an effort to improve device structure, circuit design and manufacturing methods by checking each against the others.
Siemens says existing tools such as Calibre xACT support CFET analysis. However, it has not announced which specific products will be used in this collaboration or any validation results. Support in existing tools and the results of joint research on IBM's nanostack need to be considered separately.
How does the nanostack rearrange nanosheets?
The nanostack stacks n-type and p-type transistors vertically and also offsets their positions horizontally. Conventional nanosheet devices also use stacked thin, plate-like semiconductor channels, but what the nanostack rearranges is the n-type and p-type devices themselves, which used to sit side by side. It corresponds to the CFET (complementary field-effect transistor) concept described by Siemens, and IBM takes a sequential stacking approach in which layers are built up in order.
According to IBM's structural explainer, bonding wafers to combine upper and lower devices lets more transistors fit in the same area. The n-type and p-type devices can also use different material combinations, optimized for their respective performance and power efficiency. Whether the n-type or p-type goes on top can also be chosen to suit the channel materials and manufacturing process.
This freedom comes with manufacturing conditions. Wafer flatness and alignment during bonding must be tightly controlled, and fine wiring must connect devices at multiple heights. For industrial adoption, IBM says it also needs thermally conductive bonding materials, measurement and inspection for the 3D structure, and compatible EDA development. The structure is not finished simply because it can be stacked.
Note that "0.7nm" is a name for a manufacturing generation and does not mean every part of the device is made at that dimension. What IBM is showing is a path to extending density, which has become harder to gain by packing devices closer together laterally, through vertical arrangement and material choice. Design software must reflect both that freedom and its constraints.
How to read the 50% performance gain and the SRAM shrink
The performance and power figures widely cited for the nanostack need to be read with their comparison conditions in mind. In the published abstract of research presented at VLSI 2025 by S. Reboh and colleagues, the team projects, assuming a 4-track base cell and compared with IBM's 2nm technology, roughly 50% higher performance at the same power, or roughly 70% lower power at the same performance. These are not measured values from a commercial chip achieving both at once, nor a comparison with other companies' 2nm products.
Separately, whether the structure actually works has been tested. IBM's June 25 announcement says it demonstrated operation of a CMOS inverter, a basic circuit that inverts its input, along with bonding through a thin dielectric and the design of upper and lower channels. This distinguishes evidence that stacking devices is physically viable from projections of how product-scale circuits will perform.
The SRAM shrink also has its own measured basis. A public session abstract for VLSI 2026 research by Chen Zhang and colleagues says that offsetting the upper and lower channels can cut layout cell height by more than 40% compared with advanced non-stacked cells. The structure connecting the upper and lower gates was demonstrated in silicon, but the word-line performance improvement and comparable bit-line performance are simulation results.
The reduction in cell height cannot be directly converted into an increase in cache capacity or a GPU speedup. Wiring and electrical characteristics also need to be evaluated when the smaller cells are built into circuits. Whether benefits obtained at the device and cell level can be realized in complete circuits is where design environments that handle placement and routing are tested again.
Where does the 2027 PDK sit on the road to volume production?
The PDK IBM plans to offer in January–March 2027 bundles the models, design rules, libraries and other materials needed to design circuits for a specific manufacturing process. The initial version is expected to include a standard cell library implementing logic functions and an SRAM design example. Designers can use them to try placement and routing, build early circuit blocks and evaluate potential density, power and performance.
However, IBM states clearly that the initial version will not include every model of a mature commercial PDK. It is a research kit through which fabless companies, EDA vendors, equipment makers and research institutions join early evaluation and help develop the technology and design environment together. It differs in nature from a finished release for general distribution or a design environment ready for volume orders.
Separating IBM's announcements into stages already confirmed and work still planned shows where things stand today.
| Date | What was announced | What remains |
|---|---|---|
| June 25, 2026 | Demonstration of nanostack bonding and channel design and CMOS inverter operation | Mature circuit design and manufacturing for industry. Production is expected in as little as five years. IBM announcement |
| October 13, 2026 | Plan to provide an initial research PDK in January–March 2027 | Joint evaluation using standard cells and SRAM design examples. Does not include all models of a mature commercial PDK. IBM Research |
| October 14, 2026 | Research collaboration with Siemens on design, simulation and lithography technologies | Development of virtual models and manufacturing technology. No start date for volume production has been announced. IBM announcement |
The June structural demonstration, the October design and manufacturing research, and the research PDK planned for January–March 2027 are all stages distinct from the start of volume production. The table compares official announcements about the same nanostack, and the PDK schedule is not read as a production schedule. The collaboration and the PDK are separate announcements, and it has not been confirmed that Siemens' tools or the joint research results will go into the initial PDK.
The research PDK lets designers examine the shape of circuits using the new devices early on. If wiring and thermal problems surface, that can feed back into improvements to devices and manufacturing methods. The IBM–Siemens collaboration is an effort to develop the models and technology that support this back-and-forth.
How evaluations that build circuit blocks with the initial PDK progress, and how well the resistance, capacitance and thermal models capture the real structure, will be the questions to watch. If that validation connects with improvements to bonding and wiring on the manufacturing side, the nanostack could move from a device demonstration closer to a technology designers can consider for products.