At a technology and product webinar held on October 21, 2026, Micron said it will not adopt the 4F² cell structure that has long been considered a leading candidate for next-generation DRAM. The company has researched 4F² technology for more than 20 years, but concluded that it makes manufacturing more complex, delivers benefits that do not justify the added cost, and would also limit future scaling. Micron will continue to refine the existing 6F² structure while developing 3D DRAM, which stacks memory cells, in parallel. The 4F² structure is attractive because it shrinks the area each cell occupies, but what Micron emphasizes is the size and spacing of the capacitors that hold data as an electric charge. With other companies demonstrating working 4F² structures, Micron's decision highlights the difference between being able to build a new structure and being able to mass-produce it at low cost far into the future.
A cell two-thirds the size does not automatically mean higher storage density
4F² and 6F² express the area of a memory cell, where F is the reference dimension of semiconductor microfabrication. For the same F, a 4F² cell has two-thirds the area of a 6F² cell, making it about 33% smaller. Conversely, in theory 1.5 times as many cells, or 50% more, can fit in the same area. However, this compares the geometric area of the cells; it does not mean the usable storage capacity obtained from a real semiconductor wafer increases by 50%.
A DRAM memory cell consists of a capacitor that holds data as an electric charge and a transistor that controls reading and writing. Even if the transistor can be laid out more compactly, the capacitor cannot necessarily be shrunk by the same proportion. Particularly important is the "capacitor pitch," the spacing between adjacent capacitors. Capacitors must have certain characteristics in order to retain data, and their dimensions and spacing become a constraint on how densely the whole cell can be packed.
Scott DeBoer, Micron's president and chief technology and product officer (CTPO), explained in the webinar transcript that capacitor pitch and dimensions determine DRAM bit density. According to him, once the capacitor dimensions are set, the transistor placed beneath it can be optimized in either a 6F² or a 4F² structure. In other words, a smaller cell-area figure alone does not guarantee that a higher storage density will actually be achieved. What Micron sees as the problem is how efficiently a complex structure can be manufactured while maintaining the required capacitor dimensions and spacing.
DeBoer also acknowledged that 4F² cells can be built with manufacturing technology from several generations ago. However, he noted that 4F² makes the manufacturing process more complex and raises costs, and that further scaling would run into physical problems. This explanation did not specify which physical phenomenon would be the decisive constraint. It would therefore be inaccurate to read Micron's decision as "4F² cannot be manufactured." The company did not deny that it is possible to make; it judged that there is little benefit in adopting it as a future volume-production DRAM technology.
Micron will keep scaling 6F² and develop 3D DRAM in parallel
The concrete milestone Micron laid out for future DRAM development is the start of volume production of the 1δ (1-delta) generation, planned for the second half of 2027. Slide 17 of the official presentation shows an expected bit-density improvement in the mid-20% range compared with the current 1γ (1-gamma) generation. Even without moving to 4F², the plan is to achieve further density gains by refining the existing 6F² structure.
Micron also said it will use "wafer bonding," in which separately manufactured wafers are joined together, in the following 1ε (1-epsilon) generation. According to DeBoer, later generations are also planned to introduce new materials and High-NA EUV lithography, which can form finer circuit patterns. Continuing with 6F² therefore does not mean continuing to use today's manufacturing process unchanged. The aim is to raise storage density by improving materials and manufacturing technology while keeping the basic cell structure.
Meanwhile, official slide 16 states the company's judgment that 4F² has "no viable scaling path" and sets out a policy of extending the 6F² structure while developing 3D DRAM in parallel. 3D DRAM here refers to technology that increases storage capacity per unit area by stacking the memory cells themselves. Unlike HBM (high-bandwidth memory), which stacks finished DRAM chips, it makes the cell structure three-dimensional from the start. Making the transistor vertical and stacking memory cells in multiple layers should also be considered separately.
However, Micron has not announced a specific timeline for commercializing 3D DRAM. The roadmap also carries a note that the order and positioning of the technologies shown indicate the direction of development, not actual introduction timing. Generation names and development stages may also change in the future. DeBoer explained that 3D DRAM will be developed in parallel with 6F² scaling, and that the timing of its introduction will be decided based on manufacturing cost, process complexity, and device performance. It is therefore not possible to conclude from the roadmap layout alone that the 6F² structure will end in a particular year and give way to 3D DRAM.
SK hynix demonstrates 4F² operation and addresses scaling-related challenges
While Micron has decided against 4F², SK hynix is researching DRAM built with the 4F² structure. At VLSI 2026, the company reported that it had demonstrated the electrical characteristics and read/write operation of a 4F² vertical-gate DRAM developed by Joodong Park and colleagues. According to SK hynix's research commentary, this structure places the peripheral circuitry beneath the memory cells and connects the two through wafer bonding and electrical connections between the wafers. The result points toward future high-density DRAM, but it does not demonstrate the yield or manufacturing cost needed for commercial volume production.
SK hynix's research incorporates additional measures to suppress the electrical interference that arises when cells are packed densely. One is a shared back gate placed between adjacent word lines. Word lines are the wiring used to select the cells to be read or written, and when they come close together, the electric field from an adjacent word line can affect transistor operation. The shared back gate adjusts the transistor's threshold voltage and also reduces the influence of the electric field from the neighboring word line.
This back gate can be placed without increasing cell area, but it reportedly also has adverse effects on on-current and switching characteristics. Even if interference from higher density can be suppressed, a new trade-off with transistor operating characteristics arises. Overall optimization that includes signal stability and electrical characteristics is therefore needed, not merely a smaller structure.
The bit lines used for reading present challenges as well. When bit lines come close to each other in a vertical-gate structure, parasitic capacitance between the wires increases, and adjacent signals easily become noise during reading. To address this, SK hynix placed shield structures between the bit lines. The company explains that this reduced noise from coupling between wires and cut read failures. Achieving higher density with 4F² requires countermeasures against such signal interference, not just placing cells more compactly.
Even when the name 4F² is the same, the materials used and the layout inside the cell are not necessarily the same. For example, OCTRAM, announced in 2024 by Kioxia and Nanya Technology, uses a structure in which a vertical transistor made of the oxide semiconductor InGaZnO is formed above the capacitor. This differs in vertical arrangement from the structure Micron described, in which the transistor is placed below the capacitor. Even when designs belong to the same 4F² area category, the actual manufacturing process and electrical challenges vary by design. Evaluating each company's technology therefore requires checking the specific structure and manufacturing method, not just the cell area.
What matters is manufacturing cost per good bit, not cell area
At first glance, the efforts of Micron and SK hynix look like contrasting decisions about 4F². But what the two companies are evaluating is not necessarily the same. Taking manufacturing cost and future scaling potential into account, Micron indicated it will not adopt 4F² as a volume-production technology. SK hynix, for its part, has demonstrated the electrical characteristics and read/write operation of a new 4F² structure at the research stage. In other words, Micron is choosing the technology it will mass-produce over the long term, while SK hynix is at the stage of confirming that a new structure actually works.
Organizing the announcements, the development stage and the focus of evaluation differ as follows.
| Company / technology | Announced decision or research result | Information needed for further evaluation |
|---|---|---|
| Micron (October 21, 2026 roadmap) | Will not adopt 4F²; will pursue 6F² scaling and 3D DRAM development | Specific figures for manufacturing cost and yield compared with 4F² under the same conditions have not been disclosed |
| SK hynix (VLSI 2026) | Demonstrated electrical characteristics and read/write operation in a 4F² structure using wafer bonding | Yield and manufacturing cost in commercial volume production are unconfirmed |
| Kioxia / Nanya Technology (OCTRAM, 2024) | Vertical oxide-semiconductor transistor formed above the capacitor | A research announcement, not an announcement of a mass-production product |
This comparison organizes the stage each technology is at, based on Micron's official materials and transcript and the research announcements of SK hynix and Kioxia. It is not the result of directly comparing performance or cost using DRAM of the same manufacturing generation. For example, the mid-20% bit-density improvement Micron targets for the 1δ generation and the theoretical 50% cell-density gain from changing from 6F² to 4F² are based on different comparison conditions to begin with. The former is a density-improvement target between actual manufacturing generations; the latter is merely a geometric calculation with the reference dimension F held fixed.
Adopting wafer bonding also does not depend on whether 4F² is chosen. Micron has said it will use wafer bonding in the 1ε generation that develops the 6F² structure, and SK hynix uses the same technology in its 4F² demonstration. What matters to both companies is not whether wafers are bonded, but which parts are manufactured separately and whether the resulting density and performance justify the added process complexity and cost of bonding. Wafer bonding is a manufacturing technology that can be used with different cell structures, and its effectiveness also varies with the structure adopted.
To judge which approach will prevail, it will be necessary to compare cost per good bit, yield, and required operating performance within the same manufacturing generation. Micron's planned start of 1δ volume production in the second half of 2027 will be a milestone for measuring progress in further scaling the 6F² structure. For 4F² technology, the focus will be how stable a yield and how low a manufacturing cost can be secured as it moves from research-stage demonstrations to commercial volume production.
What matters in the DRAM technology race is not shrinking the cell-area number itself. The question is how much the storage capacity that can be mass-produced rises with each generation, while maintaining required performance and holding down process complexity and cost. Micron's decision not to adopt 4F² should be seen not as a mere pick-and-choose among scaling technologies, but as part of a long-term manufacturing strategy for deciding what structure will be used to raise DRAM density going forward.