SK hynix has revealed a design that hands the repetitive work inside an SSD to about 100 small processors called H-TPUs. According to an October 12 ISOCC 2026 talk reported by Korea's The Elec, a single H-TPU consumes about 2.5% of the power of a general-purpose CPU core and takes up about 4% of the area. Rather than adding more control CPUs as SSDs get faster, the design divides the work finely and runs only the parts that are needed. Looking at what the small cores take on shows that SSD efficiency depends on more than transfer speed.
Splitting the work across about 100 small cores
H-TPU stands for Hynix Transaction Processing Unit. It handles the tasks that repeat constantly inside an SSD: processing read and write commands, updating the information used to manage data, and controlling the buffers that temporarily hold data in transit. Although the name includes "TPU," the use described this time is SSD input/output processing.
According to The Elec's on-site coverage, Injae Koo, head of SoC design at SK hynix, who gave the talk, explained that the Arm CPU cores used in conventional SSD controllers are overpowered for simple, repetitive processing. The concern is that as transfers get faster, more instructions must be processed, and adding CPUs to keep up inflates the burden on power and area.
The H-TPU narrows its instruction-processing pipeline to four stages and uses an in-order design that executes instructions in sequence. Among the small cores divided up by function, only those needed for an I/O request are run, while the rest stay idle. A general-purpose CPU is kept for error recovery and exception handling, and it still manages the policy for how data is stored.
SK hynix also reportedly prepared development tools such as a dedicated compiler. Even with the work broken into smaller pieces, each task can be written as a program. The H-TPU can be seen as a design that leaves room for software changes in small cores built for specific purposes.
The 2.5% figure compares single cores
Power at one-fortieth of a general-purpose CPU core, and area at one twenty-fifth. SK hynix's explanation as relayed by The Elec has to be read with attention to what is being compared, as the table below shows.
| Item | What was described in the talk | Basis |
|---|---|---|
| Power consumption | About 2.5% (1/40) | Single H-TPU vs. a general-purpose CPU core |
| Area | About 4% (1/25) | Single H-TPU vs. a general-purpose CPU core |
| Number of units | About 100 | H-TPUs in the SSD controller described |
| Pipeline | 4 stages | Instruction processing inside the H-TPU |
These are the company's figures as conveyed by a news report, not independent product benchmarks. The article does not state comparison conditions such as the CPU model or clock frequency, and it is unclear whether the numbers were measured on the same workload. It also gives no baseline power for the whole SSD or a breakdown by component. A drop to 2.5% at the single-core level cannot be converted into a power reduction for the SSD as a whole.
In an actual controller, many H-TPUs run and a general-purpose CPU remains. Because the design runs only the cores it needs, multiplying by the unit count would not give real operating power either. The product-level effect would have to be judged by how much power the whole SSD uses, and how much work it gets done, under the same read/write load.
Still, the significance of dividing work among small cores can be read separately from the area and power ratios. Delays that arise when management tasks and I/O processing share the same CPU are also a design problem.
What a patent shows about separating management from I/O
The U.S. patent US11675537B2, filed by SK hynix, describes a design that divides work between a CPU and a group of small processors. It is a patent publication issued in June 2023, based on a Korean application filed in November 2020. It is not a document guaranteeing the same implementation as today's H-TPU, but it offers a clue to why SSD processing is distributed this way.
An SSD does more than handle read and write requests arriving from the host. It also updates the mapping of where data is stored and performs management tasks such as garbage collection to free up space. The patent gives an example in which, if the CPU processes I/O requests only after finishing garbage collection, responses to requests are delayed and performance drops.
So the CPU is given memory management, while multiple small processors move the I/O forward. The patent explains that the CPU and the group of small processors can operate at the same time. The aim of the design is to decouple I/O from waiting on management tasks to finish.
That said, not every request can be advanced independently without conditions. In the patent's embodiment, a mechanism is also provided to notify the CPU of an exception when it detects something like a dependency on an earlier incomplete request. Normal processing proceeds on the small-processor group, and the work returns to the CPU when ordering or management decisions are needed. This division of roles supports parallel I/O processing.
The patent also describes the ability to change the firmware running on each small processor. The idea is to make the design easier to adapt to the usage environment than processing I/O with fixed circuits alone, which are hard to change. This matches the mention of a dedicated compiler in the talk: keeping programmability while specializing the processing.
The patent's structure alone cannot yield speed or latency improvement figures for this product. Even so, separating the story of shrinking cores from the story of reducing work-queue waits makes the aim of the H-TPU easier to grasp.
From enterprise SSDs to AI storage
The Elec reports that SK hynix plans to apply the H-TPU to its NAND product lineup, including next-generation enterprise SSD controllers. Also named as targets were "Storage Next," aimed at fine-grained data access, and the high bandwidth flash memory "HBF," which is planned for release in 2027. At this point, the report does not give a specific model number or release date for an H-TPU-equipped SSD.
The official abstract of Koo's talk also lists data movement, latency, and power efficiency, in addition to transfer bandwidth, as challenges brought by successive PCIe generations. In AI systems, large volumes of data move between compute, memory, and storage, so the view is that the scope of the SoC widens from individual devices to the memory system as a whole.
The place to verify the H-TPU's value will be real products, with power and performance measured under the same I/O load. If it turns out that wait times stay low even when management tasks overlap, it will be possible to judge concretely whether assigning work to small cores is a way to run fast SSDs within limited power.