On October 20, 2026, Synaptics announced the Astra SR200 series of AI processors, which use Google Research's Coral NPU. The chips pair a low-power microcontroller (MCU) with memory expandable to several hundred megabytes, with the aim of running audio and image AI processing on the device itself. On the same day, Google announced that the 32-bit Coral NPU design is complete and released a new compiler, and the two companies also expanded their development board lineup. Building AI into devices that continuously monitor sound and video requires more than raw compute performance: the memory capacity for storing models and the power consumption, including in standby, matter just as much. The SR200 is a product that tries to address these challenges at the processor design stage.
A memory design that brings image and audio AI to an MCU
The Astra SR200 series consists of three lines: the SR210 for always-on voice recognition and sensing, the SR230 for image processing and display output, and the SR250 for applications that need still higher performance. Their nominal AI compute figures are 200 GOPS, 300 GOPS, and 400 GOPS, respectively. GOPS is a unit representing one billion operations per second. The three lines are pin-compatible and support a common software development kit (SDK), so device makers can choose the performance level that suits their application while reusing their board designs and software assets.
The AI computation is handled by Synaptics' "Torq AI engine," which incorporates the Coral NPU. An NPU is a dedicated processor for running neural network computations efficiently. However, if there is not enough memory to hold the AI model's parameters and intermediate data, or if data cannot be supplied at the required speed, raising compute performance will not deliver sufficient processing speed. In its technical explanation of the architecture, Synaptics likewise says that for memory-bound workloads, simply adding compute capability does not solve the problem.
The SR200 therefore combines up to 8MB of SRAM with high-bandwidth custom DRAM that can be expanded to several hundred megabytes. According to the product brief, it uses a System in Package (SiP) approach, in which compute circuits, power management circuits, large-capacity memory, and other elements are built from multiple semiconductor dies and housed in a single package. The DRAM is not integrated on the same silicon die as the processor; rather, it is connected within the package. This is intended to secure memory capacity and bandwidth while simplifying the overall system configuration, including external components.
In its press release, Synaptics emphasizes an approach that treats memory as the foundation of system design rather than something added later. For AI processing that combines images and audio, it is important to be able to store not only the model itself but also input data and intermediate data. A key design feature of the SR200 is that it widens the scope for handling workloads that were constrained by memory capacity on conventional MCUs.
Power-saving design that separates always-on monitoring from heavy processing
The SR200 combines an Arm Cortex-M85 running at up to 800MHz with a 200MHz Cortex-M52. According to Synaptics, the Cortex-M52 continues low-power tasks such as constant monitoring; when higher compute performance is needed, the Cortex-M85 takes over the processing and returns to a dormant state afterward. A HiFi 5 DSP is also available as an option for audio processing, allowing the appropriate processing unit to be used for each task. Rather than running everything on a high-performance CPU, the design reduces power consumption by dividing roles according to the workload.
Power management is divided into four domains: always-on, ultra-low-power, low-power, and high-performance. Only the circuits needed for monitoring run continuously, and additional CPU cores and memory are brought online when more complex processing arises. For example, a device that performs image recognition only when a sensor detects a change does not need to keep its image-processing circuits in high-performance mode all the time. The key point is that even an always-on AI device does not have to run all of its circuits all the time.
Synaptics also claims that its custom DRAM can handle workloads using about one-third of the power of typical system DRAM. However, the announcement materials do not give detailed measurement conditions, such as the model of the DRAM used for comparison or the processing load. The power savings of the memory alone cannot be taken as an improvement rate for the whole device's power consumption or battery life. Judging the real-world effect requires measurements on actual hardware that include not only the CPU and NPU but also cameras, sensors, wireless communication, and other components.
The intended applications extend beyond wearables to image and audio processing in network cameras and industrial equipment. Products aimed at industrial use come with Gigabit Ethernet and two CAN-FD channels, allowing information acquired from sensors and AI processing results to be exchanged with other devices. By combining large-capacity memory with power-saving control, the concept is for a compact processor to handle everything from audio and video input to AI inference and communication between devices.
Google's published Coral NPU design and the SR200 implementation are separate things
When Google announced the Coral NPU on October 15, 2025, its matrix computation unit was still under development. In its new technical explanation, Google says that adding this unit completes the development phase of the 32-bit design. This means that design assets for efficiently handling the matrix calculations frequently used in AI inference with dedicated circuitry have now been published.
The new matrix computation unit is designed to reuse weights and input data in registers close to the compute units. What Google emphasizes is reducing not just the computation itself but the power consumed by repeatedly moving the data needed for it. Keeping data near the compute units and reusing it reduces transfers to and from memory. This idea is consistent with the SR200's approach of placing memory capacity and bandwidth at the center of processor design.
However, the overall Coral NPU design that has now been published must be distinguished from the features actually implemented in the SR200. According to Google, the SR200 uses the second-generation Coral NPU IP and supports a RISC-V vector core. But the explanation does not confirm that all features, including the newly published matrix computation unit, are implemented in the SR200. Likewise, the Coral NPU's stated target of 10mW average power consumption during inference does not represent power consumption measured on the SR200 or on the development boards as a whole.
On the software side, "Coral Compiler v1.0," built on IREE and MLIR, has been released. The compiler accepts AI models created in JAX, PyTorch, and TensorFlow, distributes processing between the CPU and NPU, and performs optimizations such as splitting large matrices into sizes that fit in memory. When operations the hardware does not support are handled on the CPU side, data handoffs and additional computation can increase latency and power consumption. Combining NPU circuit design with compiler optimization is therefore essential for efficient AI inference.
The aim of providing common development tools is to reduce the burden of redoing model conversion and operation implementation every time the chip changes. When design assets and software are public, developers also benefit from being able to inspect the internal processing and adjust it to their needs. However, because model size, supported operations, and available memory capacity differ by hardware, being able to use a common compiler does not mean a model can run without adjustment on every device.
Two types of Coralboard: one for Linux, one for MCUs
On October 20, Synaptics and Google Research also announced general availability of the "Coralboard SL" development board and unveiled a new product, the "Coralboard SR." According to Synaptics' announcement, the two products share the common Coral development environment but target different uses. The Coralboard SL is for Linux-based IoT devices and robotics, while the Coralboard SR is intended for low-power on-device AI development using MCUs. The main specifications and availability are as follows.
| Item | Coralboard SL | Coralboard SR |
|---|---|---|
| Main development target | Linux-based IoT and robotics | MCU-based on-device AI (SR200 supports Zephyr RTOS) |
| Processor | Astra SL2619 | Astra SR250 |
| Main CPUs | 2GHz Cortex-A55 × 2, Cortex-M52 | 800MHz Cortex-M85, Cortex-M52 |
| AI compute performance (nominal) | 1 TOPS | 400 GOPS |
| Memory | 2GB DDR4 | Up to 8MB SRAM, up to 256MB custom DRAM |
| Availability as of October 20, 2026 | Generally available worldwide through DigiKey | Announced as a new product; general sales start date not disclosed |
The nominal AI compute figures of the two products do not directly represent a difference in actual inference speed. They are not the result of running the same AI model under identical conditions, and the OS, memory configuration, and expected workloads also differ. In addition, the Coralboard SL is a product that uses the existing Astra SL2619, and it is a separate development board from the Coralboard SR, which uses the newly announced SR200 series. The start of general availability for the SL does not mean that boards with the SR200 can also be purchased.
What matters to developers is whether the AI model they want to run fits in the chosen memory configuration, and whether the response speed and power consumption needed to switch from constant monitoring to inference processing are met. They need to measure on actual hardware, including peripherals such as cameras and wireless communication, and check how much model optimization and adjustment will be required.
The Astra SR200 aims to let small devices handle image and audio AI processing that was difficult for conventional MCUs because of memory and power constraints. However, evaluating its practicality requires confirming not just the nominal compute performance but also the scale of models that actually run, power consumption during inference and standby, and response speed. Going forward, attention will focus on the results of validation on SR200-based devices, as well as when general availability of the Coralboard SR will begin.