GDDR6

S. Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, D. Ka, Kyu-Dong Hwang, Jeong-Joon Park, Kyeongpil Kang, Jungyeon Kim, Junyeol Jeon, N. Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jong-Hak Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Dong-Young Ko, Y. Jun, Kee-yeong Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Dae-Han Kwon, Jieun Jang, Il-Ryong Park, J. Chun, Joohwan Cho

With advances in deep-neural-network applications the increasingly large data movement through memory channels is becoming inevitable: specifically, RNN and MLP applications are memory bound and the memory is the performance bottleneck [1]. DRAM featuring processing in memory (PIM) significantly reduces data movement [1]–[4], and the system performance is enhanced by the large internal parallel bank bandwidth. Among DRAM-based PIM proposals, [3] is near commercialization, but the required HBM technology may prevent it from being applied to other applications due to its high cost [5]. In this situation, an accelerator-in-memory (AiM) based on GDDR6 may be applicable: it has a relatively low-cost, is compatible with GDDR6 interface, and is designed to accelerate deep-learning (DL) applications. AiM offers a peak throughput of 1 TFLOPS with processing units (PUs) with a speed of 1 GHz utilizing the characteristics of GDDR6 with a speed of 16Gb/s. It can also support many applications as it has various activation functions. This paper first looks at the AiM architecture and the supported command set for DL operations. Next, the DL operations in the PU and supported activation functions are described. Finally, we present evaluation results of DL behavior of AiM at the package and the system level.

Yongkee Kwon, Kornijcuk Vladimir, N. Kim, Woojae Shin, Jong-Hak Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, B. An, Jeongbin Kim, Jaewook Lee, Il-Hyu Kim, Jaehan Park, C. Park, Yosub Song, Byeongsu Yang, Hyung-Won Lee, Seho Kim, Dae-Bok Kwon, S. Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, D. Ka, K. Hwang, Jeong-Joon Park, Kyeongpil Kang, JungYeon Kim, J. Jeon, Myeong-Ok Lee, Minyoung Shin, Mi-Yea Shin, Jae-Han Cha, Chan-Hyuk Jung, K. Chang, Chunseok Jeong, Euicheol Lim, Il Park, Jun-Hyun Chun, S. Hynix

S. Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, D. Ka, Kyu-Dong Hwang, Jeong-Joon Park, Kyeongpil Kang, Jungyeon Kim, Junyeol Jeon, N. Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jong-Hak Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Dong-Young Ko, Y. Jun, Kee-yeong Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Dae-Han Kwon, Jieun Jang, Il Park, J. Chun, Joohwan Cho

In this article, a 1.25-V 8-Gb, 16-Gb/s/pin GDDR6-based accelerator-in-memory (AiM) is presented. A dedicated command (CMD) set for deep learning (DL) is introduced to minimize latency when switching operation modes, and a bank-wide mantissa shift (BWMS) scheme is adopted to minimize calculation delay time, current consumption, and circuit area during multiply-accumulate (MAC) operation. By storing the lookup table (LUT) in the reserved word line in the dynamic random access memory (DRAM) bank cell, it is possible to support various activation functions (AFs), such as Gaussian error linear unit (GELU), sigmoid, and Tanh as well as rectified linear unit (ReLU) and Leaky ReLU. Performance evaluation was conducted by measuring the fabricated chip in ATE and a self-manufactured field-programmable gate array (FPGA)-based system. In the ATE-level evaluation, it operates at 16 Gbps up to a voltage as low as 1.10 V. When evaluated by GEMV and MNIST in the FPGA-based system, it was confirmed that the performance gains of 7.5–10.5 times were possible compared to the HBM2-based or GDDR6-based systems.

Ji-Hyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gangsik Lee, Sangyeon Byeon, Boram Kim, Donghoon Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, S. Jeong, Jaehoon Cha, Mi-Lim Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joohwan Cho, J. Chun, S. Cha

The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3- $\sigma $ value of the phase skew from 4.16 to 2.25 ps.

Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, D. Kwon, C. Cho, Sang-Hoon Kim, Donggun An, C. Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-young Park, Hyoung-Joo Kim, Ho-Seok Seol, Juhwan Kim, Jungbum Shin, Gil-Young Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, ChanYong Lee, Seungseob Lee, Taejoon Park, C. Oh, H. Ban, Hyungjong Ko, H. Song, T. Oh, Sang-Joon Hwang, Kyungseob Oh, J. Choi, Jooyoung Lee

This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.