GDDR7

Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jin-Youp Cha, Seongjin Kim, Youngtaek Kim, Mi-Lim Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, S. Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sangyeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim

The increase in GPU-based AI applications, cloud-based gaming, and video streaming services has driven the need for new a graphics memory that operates at higher bandwidth and power efficiency than existing GDDR6 SDRAM, leading to the introduction of the GDDR7 standard [1]. Since performance degradation due to thermal throttling, power cost, and device reliability are major development considerations in high-power graphics applications, PAM3 signaling is applied on single-ended pins to improve bandwidth and power consumption, while maintaining the clock frequency [2]. However, new PAM3-related blocks supporting double the bandwidth inevitably increase in absolute power and temperature. In this paper, we present additional power reduction techniques, while maintaining SNR. The clocking architecture, with fast wake-up capabilities, can be partially disabled to provide active-standby current (IDD3N) as low as the power-down mode. The PAM3 TX and RX use a design approach that achieves high SNR and power efficiency.

Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Y. Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Un-Hak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, J. Ahn, Won Ju Sung, Yoontaek Jang, Hoyoung Song, H. Ban, Taewon Park, Changsik Yoo, T. Oh, SangJoon Hwang

The development of the graphics double-data-rate 7 (GDDR7) dynamic random access memory (DRAM) standard aims to overcome the constraints of its predecessor, GDDR6, in order to achieve higher speed operation. This article introduces a 16-Gb GDDR7 DRAM with three-level pulse amplitude modulation (PAM3) interface in a DRAM process. The proposed GDDR7 consists of two dies/four channels to support both two- and four-channel mode configuration. An adaptive gain-controlled feedforward equalizer (FFE) is implemented in the transmitter (TX) and data-dependent separately gain-controlled one-tap decision feedback equalizer (DFE) is proposed in the receiver (RX). In addition, the proposed ZQ calibration scheme uses alternately switched reference voltages to enhance the level mismatch ratio (RLM) of the PAM3 signaling. Moreover, low-power and low-jitter clocking techniques with a low-dropout (LDO) regulator and CMOS distribution are employed for WCK distribution; thereby, 60 mA per die of current reduction and 0.16 ps/mV of power-supply-induced jitter (PSIJ) could be achieved. The proposed GDDR7 achieves 37 Gb/s at 1.2 V and 32 Gb/s at 1.1 V with a 1z-nm DRAM technology.

Hyunsub Norbert Rie, Chang-Soo Yoon, J. Byun, Sucheol Lee, Garam Kim, J. Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, M. Jung, Gou Cha, Minjae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Ji-Sang Lee, E. Shin, Hyuk-Jun Kwon, Youngdon Choi, J. Choi, Hyungjong Ko

This paper presents a 40-Gb/s/pin single-ended PAM-4 transceiver for GDDR7. LV-POD interface that separates the internal voltage from the channel supply voltage (VDDQL) is used to reduce channel power consumption. Direct 4-tap decision feedback equalizer (DFE) with timing calibrated reset-less slicer at receiver (RX) and asymmetric bidirectional T-coil are employed to achieve the highest data-rate among the state-of-the-art DRAM I/Os. The prototype chip is fabricated in mimicked 10-nm class DRAM process using 28-nm CMOS. At sub-1V VDDQL, measured TX common eye window is 0.31UI. Measured RX shmoo has total of 162 pass ticks, each tick with the size of 5mV * 1ps and BER under 10-6. The total energy efficiency of 2.02pJ/b was achieved.

Boram Kim, Hankyu Chi, Hyeongjun Ko, Sangyeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jin-Youp Cha, Hyesoon Kim, Shinyoun Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim

Demand for high-bandwidth graphics memory is rapidly increasing for various applications such as AI, deep learning, autonomous cars, etc. To meet this demand, $\text{GDDR}6\mathrm{X}$ uses multilevel signaling (PAM4) for the first time in DRAM [1], while GDDR7 targets data-rates $28\text{Gb}/\mathrm{s}$ or higher using PAM3 signaling. However, the increased data rate incurs higher inter-symbol interference (ISI), while PAM3 is more vulnerable to ISI than PAM2 signaling. Decision feedback equalizers (DFEs) are widely used in receivers (RX) to remove post-cursor ISI without amplifying noise. A PAM3 RX, with an analog DFE, typically employs a direct feedback (DF) implementation, which must meet stringent feedback timing requirements. As the target speed increases it is challenging to reduce the feedback time to within 1 unit interval (UI) for a PAM3 RX due to the increased line parasitics and gate loading. While the loop-unrolled (LU) DFE technique mitigates feedback timing constraints, implementing a PAM3 LU DFE results in additional area and power overhead. In view of these drawbacks, this paper proposes a new type of PAM3 DFE, which combines the qualities of DF and LU DFEs to minimize area and power overhead, while also reducing the feedback time.

Kahyun Kim, Jung-Hun Park, Ha-Jung Park, Jia Park, Ji Hee Kim, Woo-Seok Choi

The trend of multi-chip modules (MCMs), die-to-die (D2D), and chiplet interfaces (e.g. UCIe) requires high-bandwidth densities while minimizing power consumption [1], [3], [4], [11]–[13]. Single-ended (SE) PAM3 signaling has been adopted in GDDR7 [2] as a high-bandwidth solution, increasing the data rate by 150%, compared to NRZ (PAM2) using the same baud rate. SE PAM3 signaling can also be applied to chiplet interfaces, but it faces challenges (Fig. 22.1.1): (1) the RX requires large-area reference-voltage $(\mathrm{V}_{\text{refp}}$ & $\mathrm{V}_{\text{refn}})$ generators. (2) Matching RX and TX references is challenging, and discrepancies result in a TX-RX reference offset. (3) TX drivers generate simultaneous switching noise (SSN) of up to a few hundred millivolts on $\mathrm{V}_{\text{DI}}$ in TX die [3]; this noise coupled to TX data and cannot be rejected by the RX, thereby degrading voltage margins. (4) Reducing channel pitch increases crosstalk, and PAM3 is $2\times$ more vulnerable to crosstalk than NRZ.