On October 13, 2026, Huawei revealed that its next-generation Kirin chip has entered testing and that results so far have met expectations. Chinese outlet Yicai (第一财经) reported on a technical briefing held at the company's Lianqiu Lake R&D Center in Shanghai. Huawei's in-house 3D stacking technology, "LogicFolding," is already in mass production in the Kirin 9050 series. For the next generation, the company plans to shrink the pitch of the contacts connecting the upper and lower circuit layers from 1.5μm to 1μm.
LogicFolding stacks circuits vertically to shorten the wiring that signals must travel through. Unlike the conventional approach of making the transistors themselves smaller, it aims to improve processing performance and power efficiency by rethinking how circuits are laid out and connected. To understand this development, it helps to distinguish between shrinking transistors and shortening the wiring between circuits.
Next-gen Kirin enters testing, while the 9050 series already mass-produces LogicFolding
Xu Songyu, who heads product management for wireless device chips in Huawei's semiconductor business, described the development status of the next-generation Kirin chip in interviews with Yicai and others.
According to Xu, when Huawei began researching LogicFolding, it was unclear not only whether the technology would deliver the expected performance gains, but also whether it could achieve sufficient yields for mass production. As development progressed, however, results at each stage met expectations, and in some areas exceeded initial projections, he said.
It is worth distinguishing between the Kirin 9050 series, which is already on the market, and the next-generation chip, "Kirin 2027," which is now being tested.
Chips using LogicFolding are already in mass production in the Kirin 9050 series. For Kirin 2027, by contrast, test results are described as meeting expectations, but mass production has not begun. Moreover, "as expected" refers to Huawei's own development targets. It does not mean the chip has been shown to outperform competitors' processors.
Huawei also described the commercialization of LogicFolding in an official announcement published on September 9, 2026. The company said it had put the "Kirin 9050 Pro" in the "Mate XT 2" smartphone, marking the first commercialization of a smartphone processor using LogicFolding.
The latest briefing can be seen as showing how Huawei is taking a technology that has already reached mass production and developing it into the next generation.
According to Yicai, cumulative shipments of Kirin-powered devices since 2023 have exceeded 100 million units. However, this figure covers all Kirin-equipped devices, not just those with the LogicFolding-based Kirin 9050 series. Nor does it indicate the production scale of the next-generation chip, so the numbers should not be conflated.
Bonding pitch shrinks from 1.5μm to 1μm as 3D stacking shortens wiring
The focus of the next-generation Kirin is the miniaturization of the connections between the upper and lower circuit layers.
Under Huawei's plan, the bonding pitch, 1.5μm in the Kirin 9050 Pro, will shrink to 1μm in the next-generation Kirin 2027. This figure does not describe the transistor manufacturing process. It refers to the spacing of the contacts that electrically connect the stacked circuits.
Narrowing the contact spacing makes it possible to place more vertical connections, giving designers more options for shortening the wiring between circuits.
LogicFolding splits circuits that were traditionally arranged on a single plane across multiple stacked layers. This lets long wiring runs across the same plane be replaced with short paths that connect directly to another layer.
The technology used to connect the upper and lower circuit layers is called "hybrid bonding." It joins insulating films to each other and metal contacts to each other with high precision, electrically connecting the stacked semiconductor layers.
Shorter wiring reduces the effects of resistance and capacitance that impede signal transmission. Huawei says these improvements can be used both to raise processing performance and to cut power consumption.
Behind this approach is the "τ (tau) scaling law" that Huawei proposed in May 2026. Traditional semiconductor development has emphasized improving performance and power efficiency by shrinking transistor dimensions. The τ scaling law, by contrast, positions shortening the time signals take to travel within a circuit as a key factor driving semiconductor progress.
LogicFolding is a technology that tries to put this idea into practice by changing circuit layout and wiring structure.
Not just more contacts, but fewer detours in the wiring
So why shrink the contact spacing in addition to stacking circuits vertically?
He Tingbo, who leads Huawei's semiconductor business, explains the reason in Section I of her preprint paper "Huawei's τ Chip Was Supposed to Melt?", published in September 2026.
When the spacing between the contacts linking the upper and lower circuits is wide, extra wiring is needed to carry signals to the contact locations. Even if the layers can be connected directly, having to take a detour to reach the contacts weakens the benefit of shorter wiring.
Long wiring increases resistance and capacitance, hurting signal speed and power consumption. A smaller bonding pitch makes it easier to place contacts where they are needed in the circuit, allowing the layers to be connected by shorter paths.
According to He's paper, the "Kirin 2026" achieves about 50 million vertical connections, of which 10 to 15 percent are used to carry signals.
The paper adds that a prototype chip for the next-generation "Kirin 2027" has already achieved a 1μm bonding pitch and more than 100 million vertical connections.
However, the figure of more than 100 million is the total number of vertical connections, and not all of them carry signals. Even so, being able to place connection points more densely is an important step that increases the freedom of circuit layout and wiring routes.
The existence of a Kirin 2027 prototype is not new information revealed for the first time here. The paper published in September already described the technical results at the prototype stage, and the October 13 briefing presented the progress of testing and the development plan toward 2027 once again.
Achieving a 1μm bonding pitch in a prototype chip and being able to stably mass-produce products using that technology need to be evaluated separately.
Mass-producing the next Kirin will require overcoming bonding precision and circuit design challenges
Narrowing the bonding pitch further requires raising semiconductor manufacturing precision another notch.
He's paper lists technical challenges for hybrid bonding, including controlling the stress generated during bonding, flattening the wafer surface, and cleaning processes.
In addition, techniques for managing wafer warpage and edge shape and for aligning the upper and lower layers with extremely high precision are indispensable.
The smaller the bonding pitch, the more even slight misalignment or surface defects can affect bond quality. To make use of finer contacts in actual products, manufacturing precision and stability must be improved along with design technology.
The performance gains from LogicFolding also vary depending on the type of circuit.
In Section V of the paper, He explains that the effect of LogicFolding differs between circuits well suited to parallel processing and those that are hard to parallelize.
High-performance CPU cores, which demand strong single-thread performance, are an area where improvement through parallelization is difficult. Applying LogicFolding there therefore requires meticulous circuit design, advanced EDA tools, and long periods of verification, according to the paper.
EDA is a general term for software that supports the design and verification of semiconductor circuits.
In other words, narrowing the bonding pitch and adding vertical connections will not automatically speed up every kind of processing. The design itself, meaning how circuits are divided among layers and which parts are connected, determines whether performance improves.
The paper referenced here is a preprint by a Huawei development lead and should be distinguished from independent third-party performance evaluations.
At the October 13 briefing reported by Yicai, no specific performance scores for the Kirin 2027's CPU or GPU were presented, nor were measurement conditions for comparison with other products.
Therefore, the information that the bonding pitch will shrink from 1.5μm to 1μm alone does not allow us to judge how much real-world smartphone processing speed or battery life will improve.
Expansion to mid- and low-priced devices depends on product demand
Huawei has also not yet laid out a clear policy on which price tiers will use LogicFolding in the future.
Xu Songyu said that whether to extend the technology to mid- and low-priced products will be decided according to future product demand.
Even if a technology has been put into practical use in a high-performance flagship processor, adopting the same structure is not necessarily optimal for products that must keep costs down. Whether to adopt it must be judged product by product, considering required performance, power consumption, manufacturing cost, and other factors.
The real value of Kirin 2027 will be shown by actual performance and mass-production results
Following the commercialization of LogicFolding, Huawei says it has also achieved a smaller bonding pitch and more vertical connections in its next-generation Kirin prototype. This suggests that the company's technology strategy, which raises semiconductor performance through circuit stacking and shorter wiring rather than relying solely on transistor miniaturization, is moving to its next stage.
However, what has been disclosed so far consists mainly of technical results at the prototype stage and Huawei's own assessments.
For the Kirin 2027, the key questions will be how much the design with a 1μm bonding pitch can actually improve the processing performance and power consumption of the CPU, GPU, NPU, and other components. Evaluating that effect properly will also require performance data with clearly stated measurement conditions.
Whether such fine bonding structures can be mass-produced with stable quality will also matter.
Once performance measurements from real products and mass-production results are available, it will be possible to judge more concretely whether LogicFolding remains a one-generation technology or becomes established as a foundation for continued performance gains in the Kirin series.