Ryzen 9 9950X3D

Z. ElSayed, Nelly Elsayed, Ahmed Abdelgawad

As computing power advances, the environmental cost of semiconductor manufacturing and operation has become a critical concern. However, current sustainability metrics fail to quantify carbon emissions at the transistor level, the fundamental building block of modern processors. This paper introduces a Carbon Per Transistor (CPT) formula -- a novel approach and green implementation metric to measuring the CO$_2$ footprint of semiconductor chips from fabrication to end-of-life. By integrating emissions from silicon crystal growth, wafer production, chip manufacturing, and operational power dissipation, the CPT formula provides a scientifically rigorous benchmark for evaluating the sustainability of computing hardware. Using real-world data from Intel Core i9-13900K, AMD Ryzen 9 7950X, and Apple M1/M2/M3 processors, we reveal a startling insight-manufacturing emissions dominate, contributing 60-125 kg CO$_2$ per CPU, far exceeding operational emissions over a typical device lifespan. Notably, Apple's high-transistor-count M-series chips, despite their energy efficiency, exhibit a significantly larger carbon footprint than traditional processors due to extensive fabrication impact. This research establishes a critical reference point for green computing initiatives, enabling industry leaders and researchers to make data-driven decisions in reducing semiconductor-related emissions and get correct estimates for the green factor of the information technology process. The proposed formula paves the way for carbon-aware chip design, regulatory standards, and future innovations in sustainable computing.

Sanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, P. Mercati, Nathaniel D. Bastian, Mohsen Imani

Hyperdimensional computing (HDC) suits memory, energy, and reliability-constrained systems, yet the standard "one prototype per class" design requires ${\mathcal{O}}(CD)$ memory (with C classes and dimensionality D). Prior compaction reduces D (feature axis), improving storage/compute but weakening robustness. We introduce LogHD, a logarithmic class-axis reduction that replaces the C per-class prototypes with n≈⌈logk C⌉ bundle hypervectors (alphabet size k) and decodes in an n-dimensional activation space, cutting memory to ${\mathcal{O}}\left({D{{\log }_k}C}\right)$ while preserving D. LogHD uses a capacity-aware codebook and profile-based decoding, and composes with feature-axis sparsification. Across datasets and injected bit flips, LogHD attains competitive accuracy with smaller models and higher resilience at matched memory. Under equal memory, it sustains target accuracy at roughly 2.5–3.0× higher bit-flip rates than feature-axis compression; an ASIC instantiation delivers 498× energy efficiency and 62.6× speedup over an AMD Ryzen 9 9950X and 24.3×/6.58× over an NVIDIA RTX 4090, and is 4.06× more energy-efficient and 2.19× faster than a feature-axis HDC ASIC baseline.

Derek Li, Yecheng Zhang, B. Baas

The JPEG image compression algorithm consists of multiple sub-functions that are generally easy to parallelize except for the Huffman decoder, which is fundamentally serial and thus is a throughput bottleneck in high-speed designs. Fine-grain many-core processor arrays have delivered highlyefficient computing for a variety of multimedia and embedded applications and are therefore promising platforms for JPEG decoding. Two C++ many-core Huffman decoder implementations that utilize fine-grain task-level parallelism are developed and measured executing on the 32 nm KiloCore chip. Results are compared with three commercial chips: the AMD Ryzen 9 5900x, Intel i5-12600k, and Intel i7-1165G7. All processors are measured decoding 25 4K-resolution images compressed using baseline Huffman tables. The many-core implementations achieve a scaled throughput per chip area that is $80 \times, 51 \times$, and $82 \times$ greater, and a scaled energy efficiency (codewords per unit energy) $426 \times$, $959 \times$, and $1056 \times$ greater than the Intel 1165G7, Intel 12600k, and AMD 5900x, respectively. Combining energy, throughput, and area metrics, the many-core implementations achieve $9330 \times$, $\mathbf{1 3 6 0 0} \times$, and $\mathbf{2 3 5 0 0} \times$, lower energy-delay product normalized to area, compared to the Intel 1165G7, Intel 12600k, and AMD 5900x, respectively.

A. Schmidt

O. Barkovska, Tetiana Filimonchuk, Dmytro Nikolaienko

This paper presents a performance study of the Farneback algorithm for optical flow tracking in video and images. With the growing need for efficient video processing technologies, optical flow analysis plays a critical role in fields such as sports, medicine, gaming, and smart home systems. The study compares the performance of the Farneback algorithm on different computing architectures, specifically focusing on a CPU (AMD Ryzen 9 4900H) and a GPU (nVidia GeForce GTX 1660 Ti). The results demonstrate that GPU-based parallel computing significantly enhances the speed and efficiency of the algorithm, achieving speed improvements of up to 8.791 times compared to CPU processing, particularly in real-time applications with varying video complexities. For example, videos processed with a static camera and a small number of moving objects showed a frame rate increase from 0.953 frames per second on CPU to 7.431 frames per second on GPU. The study provides insights into the practical implications of using GPUs for optical flow analysis, emphasizing their superiority in processing high-complexity video data compared to traditional CPU-based systems. These findings are crucial for developing more responsive and energy-efficient systems in real-world applications. Future research will explore broader hardware configurations and further optimization of optical flow algorithms to enhance their applicability in diverse scenarios.