DDR4

Nureddin Kamadan, Walter Wang, S. V. Schaik, Christina Garman, Daniel Genkin, Y. Yarom

Andrea Galimberti, Gabriele Montanaro, Andrea Motta, Federico Proverbio, Davide Zoni

FPGAs are increasingly utilized in data centers due to their ability to exploit parallelism in computationally intensive workloads. Modern workloads demand the transfer of vast amounts of information, making it essential to optimize communication between FPGAs and memory. This paper introduces a novel benchmarking platform for evaluating DDR4 memory performance in data-center-class FPGAs. The proposed solution features highly configurable traffic generation with complex memory access patterns defined at run time and can be flexibly instantiated on the target FPGA to support multiple memory channels and varying data rates. An extensive experimental campaign targets the AMD Kintex UltraScale 115 FPGA, encompassing up to three memory channels with data rates ranging from 1600 to 2400 MT/s. The results demonstrate the benchmaking platform’s capability to effectively evaluate DDR4 performance across various memory traffic configurations.

Vineet Chadalavada, Naseeruddin Lodge, D. Aklekar, F. Saqib

Multi-tenant FPGA cloud platforms present serious security challenges due to the shared nature of hardware resources, particularly memory. One major security risk in such environments is the threat of side-channel attacks. This work demonstrates that the Prime+Probe attack, traditionally implemented to target CPU caches, can be adapted to DDR4 memory by taking advantage of timing variations caused by contention at the row buffer level. By creating controlled memory conflicts using custom attacker and victim kernels on a Xilinx Alveo U250 accelerator, we measured variations in memory access latency that revealed the victim's access to specific memory rows. These timing variations expose access behavior and enable inference of memory usage patterns, even without shared memory or runtime interaction between the attacker and victim. Our results demonstrate that DDR4 memory, when shared between tenants, can leak information through timing-based side channels. The findings point to the need for stronger isolation strategies and improved resource management to secure multi-tenant FPGA systems against such vulnerabilities.

Ali Abbasi, Danesh Germchi, Amin Katani, Mohamed Hassan, R. Pellizzoni

We propose OpenDRAM, a synthesizable high-performance DDR4 DRAM soft Memory Controller (MC) for FPGAs. Since DRAMs usually operate at a higher frequency compared to MCs (usually \(4\times\) ), to fully utilize DRAM’s bandwidth, the hardened DDR4 physical interface expects the controller to issue four DRAM commands in a single clock cycle. OpenDRAM is a modular, extensible MC, implementing high-performance bank-parallel schedulers. We detail the design of OpenDRAM’s logic blocks in RTL and their integration with existing AMD’s Memory Interface Generator (MIG) modules for initialization, maintenance, and interfacing. The integrated project was comprehensively validated on an AMD Virtex UltraScale+ FPGA. We evaluate and compare the performance of OpenDRAM with AMD’s MIG controller and another open source controller, OPRECOMP, using synthetic and accelerator kernels. Results show that OpenDRAM surpasses both commercial and open source counterparts, offering performance improvements of up to 157% over AMD’s MIG and 267% over OPRECOMP, primarily owing to its reordering and scheduling mechanisms. To demonstrate its research use case, we prototype five distinct command schedulers, exploring tradeoffs between scheduling aggressiveness and maximum frequency, and show how FPGA-aware design can enhance timing closure. Finally, we release OpenDRAM as the first high-performance, extensible, open source MC for researchers to utilize, extend, and build upon.

Vineet Chadalavada, Nahush Tambe, D. Aklekar, F. Saqib

Multi-tenant FPGA cloud platforms face significant security challenges due to the shared use of hardware resources, particularly off-chip DDR4 memory. Timing-based side channels, such as Prime+Probe, allow adversaries to exploit row buffer contention and infer victim activity, threatening the isolation guarantees of cloud systems. In this work, we extend the Prime+Probe framework on a Xilinx Alveo U250 FPGA to evaluate countermeasures against DDR4 timing leakage. We implement three techniques: bank isolation, cache buffering, and noise injection, all of which can be applied entirely at the kernel level without hardware or cloud-level modifications. Our experimental results show that when deployed together, these defenses significantly suppress timing-based information leakage. This study provides quantitative evidence of mitigation effectiveness and offers practical strategies for securing FPGA cloud platforms against memory-level side-channel attacks.